A novel scheduling algorithm for phase change memory based main memory system with multiple ranks

2016 ◽  
Author(s):  
M J Raghunathan ◽  
V B Arjun ◽  
K S Kaushik ◽  
N Ramasubramanian
Keyword(s):  
Phase Change ◽  
Scheduling Algorithm ◽  
Phase Change Memory ◽  
Memory System ◽  
Main Memory ◽  
Change Memory

Scalable high performance main memory system using phase-change memory technology

2009 ◽  
Vol 37 (3) ◽  
pp. 24-33 ◽  
Author(s):  
Moinuddin K. Qureshi ◽  
Vijayalakshmi Srinivasan ◽  
Jude A. Rivers
Keyword(s):  
Phase Change ◽  
High Performance ◽  
Phase Change Memory ◽  
Memory System ◽  
Main Memory ◽  
Change Memory

scholarly journals Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 626
Author(s):  
Jeong Beom Hong ◽  
Young Sik Lee ◽  
Yong Wook Kim ◽  
Tae Hee Han
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Random Access ◽  
Main Memory ◽  
Data Mapping ◽  
Storage Density ◽  
Ternary Data ◽  
And Performance ◽  
Parallel Encoding ◽  
Change Memory

Multi-level cell (MLC) phase-change memory (PCM) is an attractive solution for next-generation memory that is composed of resistance-based nonvolatile devices. MLC PCM is superior to dynamic random-access memory (DRAM) with regard to scalability and leakage power. Therefore, various studies have focused on the feasibility of MLC PCM-based main memory. The key challenges in replacing DRAM with MLC PCM are low reliability, limited lifetime, and long write latency, which are predominantly affected by the most error-vulnerable data pattern. Based on the physical characteristics of the PCM, where the reliability depends on the data pattern, a tri-level-cell (3LC) PCM has significantly higher performance and lifetime than a four-level-cell (4LC) PCM. However, a storage density is limited by binary-to-ternary data mapping. This paper introduces error-vulnerable pattern-aware binary-to-ternary data mapping utilizing 3LC PCM without an error-correction code (ECC) to enhance the storage density. To mitigate the storage density loss caused by the 3LC PCM, a two-way encoding is applied. The performance degradation is minimized through parallel encoding. The experimental results demonstrate that the proposed method improves the storage density by 17.9%. Additionally, the lifetime and performance are enhanced by 36.1% and 38.8%, respectively, compared with those of a 4LC PCM with an ECC.

A durable and energy efficient main memory using phase change memory technology

2009 ◽  
Vol 37 (3) ◽  
pp. 14-23 ◽  
Author(s):  
Ping Zhou ◽  
Bo Zhao ◽  
Jun Yang ◽  
Youtao Zhang
Keyword(s):  
Phase Change ◽  
Energy Efficient ◽  
Phase Change Memory ◽  
Main Memory ◽  
Change Memory
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