Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation

2004 ◽  
Author(s):  
G. Sohi
Keyword(s):  
Computer Architecture ◽  
Chip Multiprocessors ◽  
Single Chip

Research on highly parallel embedded control system design and implementation method

Impact ◽  
2019 ◽  
Vol 2019 (10) ◽  
pp. 44-46
Author(s):  
Masato Edahiro ◽  
Masaki Gondo
Keyword(s):  
Computer Architecture ◽  
Intelligent Systems ◽  
Large Scale ◽  
General Purpose ◽  
Heterogeneous Structure ◽  
Single Chip ◽  
Powertrain Control ◽  
Processing Power ◽  
Hardware Description ◽  
Many Core

The pace of technology's advancements is ever-increasing and intelligent systems, such as those found in robots and vehicles, have become larger and more complex. These intelligent systems have a heterogeneous structure, comprising a mixture of modules such as artificial intelligence (AI) and powertrain control modules that facilitate large-scale numerical calculation and real-time periodic processing functions. Information technology expert Professor Masato Edahiro, from the Graduate School of Informatics at the Nagoya University in Japan, explains that concurrent advances in semiconductor research have led to the miniaturisation of semiconductors, allowing a greater number of processors to be mounted on a single chip, increasing potential processing power. 'In addition to general-purpose processors such as CPUs, a mixture of multiple types of accelerators such as GPGPU and FPGA has evolved, producing a more complex and heterogeneous computer architecture,' he says. Edahiro and his partners have been working on the eMBP, a model-based parallelizer (MBP) that offers a mapping system as an efficient way of automatically generating parallel code for multi- and many-core systems. This ensures that once the hardware description is written, eMBP can bridge the gap between software and hardware to ensure that not only is an efficient ecosystem achieved for hardware vendors, but the need for different software vendors to adapt code for their particular platforms is also eliminated.

scholarly journals Shared vs. snoop: Evaluation of cache structure for single-chip multiprocessors

1997 ◽  
pp. 793-797 ◽  
Author(s):  
Toru Kisuki ◽  
Masaki Wakabayashi ◽  
Junji Yamamoto ◽  
Keisuke Inoue ◽  
Hideharu Amano
Keyword(s):  
Chip Multiprocessors ◽  
Single Chip

scholarly journals An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography

2009 ◽  
Vol 2009 ◽  
pp. 1-14 ◽  
Author(s):  
Xinyu Li ◽  
Omar Hammami
Keyword(s):  
Signal Processing ◽  
Embedded System ◽  
High Performance ◽  
Chip Multiprocessors ◽  
Parallel Implementation ◽  
Data Encryption ◽  
Design Flow ◽  
Automatic Design ◽  
Single Chip ◽  
Data Parallel

Embedded system design is increasingly based on single chip multiprocessors because of the high performance and flexibility requirements. Embedded multiprocessors on FPGA provide the additional flexibility by allowing customization through addition of hardware accelerators on FPGA when parallel software implementation does not provide the expected performance. And the overall multiprocessor architecture is still kept for additional applications. This provides a transition to software only parallel implementation while avoiding pure hardware implementation. An automatic design flow is proposed well suited for data flow signal processing exhibiting both pipelining and data parallel mode of execution. Fork-Join model-based software parallelization is explored to find out the best parallelization configuration. C-based synthesis coprocessor is added to improve performance with more hardware resource usage. The Triple Data Encryption Standard (TDES) cryptographic algorithm on a 48-PE single-chip distributed memory multiprocessor is selected as an application example of the flow.

Multi-Core Architecture and Network on Chip: Applications and Challenges

2020 ◽  
Vol 17 (1) ◽  
pp. 239-245
Author(s):  
Maddula N. V. Sesha Saiteja ◽  
K. Sai Sumanth Reddy ◽  
D. Radha ◽  
Minal Moharir
Keyword(s):  
Computer Architecture ◽  
Network On Chip ◽  
Single Chip ◽  
Computing Technology ◽  
Core Technology ◽  
Multiple Cores ◽  
Research Problems ◽  
On Chip ◽  
Many Core ◽  
Day By Day

Technology improves performance and reduces in size day by day. Reduction in size can increase the density and which in turn can improve the performance. These statements suit very well for the computer architecture improvement. The whole System on Chip (SoC) brought the concept of multiple cores on a single chip. The multi-core or many-core architectures are the future of computing. Technology has improved in reducing the size and increasing the density, but improving the performance to an expectation of including more cores is a challenge of many-core technology. Utilization of all cores and improving the performance of execution by these cores are the challenges to be addressed in a many-core technology. This paper discusses the basics of many core architecture, comparison and applications. Further, it covers the basics of Network on Chip (NoC), architectural components, and various views of current Network on Chip research problems. Research problems include improving the performance of communication by avoiding congested path in routing.

Migration in Single Chip Multiprocessors

2002 ◽  
Vol 1 (1) ◽  
pp. 12-12 ◽  
Author(s):  
K.A. Shaw ◽  
W.J. Dally
Keyword(s):  
Chip Multiprocessors ◽  
Single Chip

Are single-chip multiprocessors in reach?

2001 ◽  
Vol 18 (1) ◽  
pp. 82-89 ◽  
Author(s):  
R. Bergamaschi ◽  
I. Bolsens ◽  
R. Gupta ◽  
R. Harr ◽  
A. Jerraya ◽  
...  
Keyword(s):  
Chip Multiprocessors ◽  
Single Chip
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