Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure

Register file reliability enhancement through adjacent narrow-width exploitation

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis.2016.7483882 ◽

2016 ◽

Cited By ~ 2

Author(s):

Hamzeh Ahangari ◽

Ihsen Alouani ◽

Ozcan Ozturk ◽

Smail Niar ◽

Atika Rivenq

Keyword(s):

Register File ◽

Narrow Width ◽

Reliability Enhancement

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In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability

International Conference on Dependable Systems and Networks (DSN'06) ◽

10.1109/dsn.2006.43 ◽

2006 ◽

Cited By ~ 5

Author(s):

Jie Hu ◽

Shuai Wang ◽

S.G. Ziavras

Keyword(s):

Register File ◽

Narrow Width

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Exploiting narrow-width values for thermal-aware register file designs

2009 Design, Automation & Test in Europe Conference & Exhibition ◽

10.1109/date.2009.5090887 ◽

2009 ◽

Cited By ~ 1

Author(s):

Shuai Wang ◽

Jie Hu ◽

S.G. Ziavras ◽

Sung Woo Chung

Keyword(s):

Register File ◽

Narrow Width

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On the Exploitation of Narrow-Width Values for Improving Register File Reliability

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2009.2017441 ◽

2009 ◽

Vol 17 (7) ◽

pp. 953-963 ◽

Cited By ~ 12

Author(s):

Jie Hu ◽

Shuai Wang ◽

S.G. Ziavras

Keyword(s):

Register File ◽

Narrow Width

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Instruction Scheduling Algorithm for Register File Connectivity Clustered VLIW Architecture

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2008.00127 ◽

2009 ◽

Vol 31 (1) ◽

pp. 127-132

Author(s):

Zhi-Xiong ZHOU ◽

Hu HE ◽

Xu YANG ◽

Yan-Jun ZHANG ◽

Yi-He SUN

Keyword(s):

Scheduling Algorithm ◽

Instruction Scheduling ◽

Register File

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Active-Cycle Based Register File Design for Reduced Ports and Energy

Chinese Journal of Computers ◽

10.3724/sp.j.1016.2008.00299 ◽

2009 ◽

Vol 31 (2) ◽

pp. 299-308 ◽

Cited By ~ 1

Author(s):

Yu-Lai ZHAO ◽

Xian-Feng LI ◽

Dong TONG ◽

Han-Xin SUN ◽

Jie CHEN ◽

...

Keyword(s):

Register File ◽

File Design

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Register/ file/ cache microarchitecture study using VHDL

Proceedings of the 24th annual international symposium on Microarchitecture - MICRO 24 ◽

10.1145/123465.123510 ◽

1991 ◽

Author(s):

Samarina Makhdoom ◽

Daniel Tabak ◽

Richard Auletta

Keyword(s):

Register File ◽

File Cache

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24.4 A 5nm [email protected] and [email protected] 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue

2021 IEEE International Solid- State Circuits Conference (ISSCC) ◽

10.1109/isscc42613.2021.9366000 ◽

2021 ◽

Author(s):

Hidehiro Fujiwara ◽

Yi-Hsin Nien ◽

Chih-Yu Lin ◽

Hsien-Yu Pan ◽

Hao-Wen Hsu ◽

...

Keyword(s):

Standard Cell ◽

Register File

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A 0.13 μm 6 GHz 256×32b leakage-tolerant register file

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) ◽

10.1109/vlsic.2001.934182 ◽

2002 ◽

Author(s):

R. Krishnamurthy ◽

A. Alvandpour ◽

G. Balamurugan ◽

N. Shanbhagh ◽

K. Soumyanath ◽

...

Keyword(s):

Register File

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A study of inverse narrow width effect of 65nm low power CMOS technology

2008 9th International Conference on Solid-State and Integrated-Circuit Technology ◽

10.1109/icsict.2008.4734750 ◽

2008 ◽

Cited By ~ 10

Author(s):

Liu Xinfu ◽

Lim Kheeyong ◽

Wu Zhihua ◽

Xiong Zhibin ◽

Ding Yongping ◽

...

Keyword(s):

Low Power ◽

Cmos Technology ◽

Width Effect ◽

Low Power Cmos ◽

Narrow Width

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