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Keyword(s):  
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A scalable register file architecture for superscalar processors

1998 ◽  
Vol 22 (1) ◽  
pp. 49-60
Author(s):  
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Nader Bagherzadeh
Keyword(s):  
Superscalar Processors ◽  
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Instruction Scheduling Algorithm for Register File Connectivity Clustered VLIW Architecture

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Vol 31 (1) ◽  
pp. 127-132
Author(s):  
Zhi-Xiong ZHOU ◽  
Hu HE ◽  
Xu YANG ◽  
Yan-Jun ZHANG ◽  
Yi-He SUN
Keyword(s):  
Scheduling Algorithm ◽  
Instruction Scheduling ◽  
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2009 ◽  
Vol 31 (2) ◽  
pp. 299-308 ◽  
Author(s):  
Yu-Lai ZHAO ◽  
Xian-Feng LI ◽  
Dong TONG ◽  
Han-Xin SUN ◽  
Jie CHEN ◽  
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scholarly journals High-bandwidth data memory systems for superscalar processors

1991 ◽  
Vol 26 (4) ◽  
pp. 53-62 ◽  
Author(s):  
Gurindar S. Sohi ◽  
Manoj Franklin
Keyword(s):  
Memory Systems ◽  
Superscalar Processors ◽  
Data Memory ◽  
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2002 ◽  
Author(s):  
R. Krishnamurthy ◽  
A. Alvandpour ◽  
G. Balamurugan ◽  
N. Shanbhagh ◽  
K. Soumyanath ◽  
...  
Keyword(s):  
Register File
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