Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design

Fatih Hamzaoglu; Yih Wang; Pramod Kolar; Liqiong Wei; Yong-Gee Ng; Uddalak Bhattacharya; Kevin Zhang

doi:10.1109/mdt.2011.5

Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design

IEEE Design & Test of Computers ◽

10.1109/mdt.2011.5 ◽

2011 ◽

Vol 28 (1) ◽

pp. 22-31 ◽

Cited By ~ 16

Author(s):

Fatih Hamzaoglu ◽

Yih Wang ◽

Pramod Kolar ◽

Liqiong Wei ◽

Yong-Gee Ng ◽

...

Keyword(s):

Sram Design ◽

Circuit Techniques ◽

Nanoscale Sram

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CAD and Circuit Techniques for Ultra Low Power, Variation-Aware SRAM Design

10.18130/v37m2f ◽

2014 ◽

Author(s):

Peter Beshay

Keyword(s):

Low Power ◽

Ultra Low Power ◽

Power Variation ◽

Sram Design ◽

Circuit Techniques

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Preface to the Special Issue on ^|^ldquo;Electronic Circuit Techniques in the Power Saving Era^|^rdquo;

IEEJ Transactions on Electronics Information and Systems ◽

10.1541/ieejeiss.133.219 ◽

2013 ◽

Vol 133 (2) ◽

pp. 219-219

Author(s):

Akira Hyogo

Keyword(s):

Electronic Circuit ◽

Power Saving ◽

Special Issue ◽

Circuit Techniques

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A Single Amplifier-Based 12-bit 100MS/s 1V 19mW 0.13µm CMOS ADC with Various Power and Area Minimized Circuit Techniques

IEICE Transactions on Electronics ◽

10.1587/transele.e94.c.1282 ◽

2011 ◽

Vol E94-C (8) ◽

pp. 1282-1288 ◽

Cited By ~ 4

Author(s):

Byeong-Woo KOO ◽

Seung-Jae PARK ◽

Gil-Cho AHN ◽

Seung-Hoon LEE

Keyword(s):

Circuit Techniques

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Circuit Techniques for High Efficiency Fully-Integrated Switched-Capacitor Converters

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2020.3046514 ◽

2020 ◽

pp. 1-1

Author(s):

Junmin Jiang ◽

Xun Liu ◽

Wing-Hung Ki ◽

Philip K. T. Mok ◽

Yan Lu

Keyword(s):

High Efficiency ◽

Switched Capacitor ◽

Fully Integrated ◽

Circuit Techniques

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Buried Bitline for sub-5nm SRAM Design

2020 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm13553.2020.9372042 ◽

2020 ◽

Author(s):

R. Mathur ◽

M. Bhargava ◽

S. Salahuddin ◽

P. Schuddinck ◽

J. Ryckaert ◽

...

Keyword(s):

Sram Design

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State-of-the-art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401059 ◽

2021 ◽

Author(s):

Woorham Bae

Keyword(s):

State Of The Art ◽

Phase Locked Loops ◽

Extensive Survey ◽

Performance Benchmark ◽

Low Jitter ◽

Circuit Techniques

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Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques

2012 25th International Conference on VLSI Design ◽

10.1109/vlsid.2012.32 ◽

2012 ◽

Author(s):

P. Hanumolu ◽

U. Moon ◽

T. Fiez

Keyword(s):

Signal System ◽

Mixed Signal ◽

Circuit Techniques

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A 5nm Wide Voltage Range Ultra High Density SRAM Design for L2/L3 Cache Applications

2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID) ◽

10.1109/vlsid51830.2021.00031 ◽

2021 ◽

Author(s):

Sriharsha Enjapuri ◽

Deepesh Gujjar ◽

Sandipan Sinha ◽

Ramesh Halli ◽

Manish Trivedi

Keyword(s):

High Density ◽

Voltage Range ◽

Sram Design

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Embedded SRAM design in deep deep submicron technologies

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference ◽

10.1109/esscirc.2007.4430324 ◽

2007 ◽

Cited By ~ 7

Author(s):

W. Dehaene ◽

S. Cosemans ◽

A. Vignon ◽

F. Catthoor ◽

P. Geens

Keyword(s):

Deep Submicron ◽

Sram Design ◽

Embedded Sram

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Dynamic Data Stability in Low-power SRAM Design

2007 IEEE Custom Integrated Circuits Conference ◽

10.1109/cicc.2007.4405722 ◽

2007 ◽

Cited By ~ 6

Author(s):

M. Sharifkhani ◽

S. M. Jahinuzzaman ◽

M. Sachdev

Keyword(s):

Low Power ◽

Dynamic Data ◽

Sram Design

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