Subword Switching Activity Minimization to Optimize Dynamic Power Consumption

2009 ◽  
Vol 26 (4) ◽  
pp. 68-77
Author(s):  
M.C. Molina ◽  
R. Ruiz-Sautua ◽  
A. Del Barrio ◽  
J.M. Mendias
Keyword(s):  
Power Consumption ◽  
Switching Activity ◽  
Dynamic Power

scholarly journals Clock Gating Flip-Flop using Embedded XoR Circuitry

2021 ◽  
Author(s):  
Peiyi Zhao ◽  
William Cortes ◽  
Congyi Zhu ◽  
Tom Springer
Keyword(s):  
Power Consumption ◽  
Switching Activity ◽  
Clock Gating ◽  
Flip Flop ◽  
Dynamic Power ◽  
Data Switching

Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption. In this paper, a novel flip-flop (FF) using clock gating circuitry with embedded XOR, GEMFF, is proposed. Using post layout simulation with 45nm technology, GEMFF outperforms prior stateof-the-art flip-flop by 25.1% at 10% data switching activity in terms of power consumption.

scholarly journals Performance of rc low encoding techniques for reducing coupling transitions

2018 ◽  
Vol 7 (4.20) ◽  
pp. 36
Author(s):  
Shavali. V ◽  
Dr. Sreerama Reddy G.M ◽  
Dr. Ramana Reddy.P
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Propagation Delay ◽  
Total Power ◽  
Switching Activity ◽  
Dynamic Power ◽  
Delay Propagation ◽  
Total Power Consumption ◽  
Simulation Results ◽  
Data Buses

RC Network has delay propagation by wire and dynamic power dissipation. Basically it can perform two encoding techniques. They are Firstly it will reduce more dynamic power dissipation and delay propagation of wire simultaneously. Its simulation results of coupling activity  and switching activity is more when the input is in Toggle state on 8-bit  and for  32-bit data buses It increases. To reduce dynamic power is bus and total propagation delay  the encoding techniques is Introduced which reduces coupling Coupling transitions, Dynamic power. Secondly it will also reduce more total power consumption when Width of Bus and Length of Bits Increases Its coupling activity is Reduced Gradually when the Data moves for one state to another State and switching activity is Reduced  

scholarly journals Towards an Efficient CNN Inference Architecture Enabling In-Sensor Processing

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 1955
Author(s):  
Md Jubaer Hossain Pantho ◽  
Pankaj Bhowmik ◽  
Christophe Bobda
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Image Sensor ◽  
Machine Learning Algorithms ◽  
Hierarchical Optimization ◽  
Computation Method ◽  
Optimization Approach ◽  
Efficient Computation ◽  
Feature Maps ◽  
Dynamic Power

The astounding development of optical sensing imaging technology, coupled with the impressive improvements in machine learning algorithms, has increased our ability to understand and extract information from scenic events. In most cases, Convolution neural networks (CNNs) are largely adopted to infer knowledge due to their surprising success in automation, surveillance, and many other application domains. However, the convolution operations’ overwhelming computation demand has somewhat limited their use in remote sensing edge devices. In these platforms, real-time processing remains a challenging task due to the tight constraints on resources and power. Here, the transfer and processing of non-relevant image pixels act as a bottleneck on the entire system. It is possible to overcome this bottleneck by exploiting the high bandwidth available at the sensor interface by designing a CNN inference architecture near the sensor. This paper presents an attention-based pixel processing architecture to facilitate the CNN inference near the image sensor. We propose an efficient computation method to reduce the dynamic power by decreasing the overall computation of the convolution operations. The proposed method reduces redundancies by using a hierarchical optimization approach. The approach minimizes power consumption for convolution operations by exploiting the Spatio-temporal redundancies found in the incoming feature maps and performs computations only on selected regions based on their relevance score. The proposed design addresses problems related to the mapping of computations onto an array of processing elements (PEs) and introduces a suitable network structure for communication. The PEs are highly optimized to provide low latency and power for CNN applications. While designing the model, we exploit the concepts of biological vision systems to reduce computation and energy. We prototype the model in a Virtex UltraScale+ FPGA and implement it in Application Specific Integrated Circuit (ASIC) using the TSMC 90nm technology library. The results suggest that the proposed architecture significantly reduces dynamic power consumption and achieves high-speed up surpassing existing embedded processors’ computational capabilities.

scholarly journals Idleness-Aware Dynamic Power Mode Selection on the i.MX 7ULP IoT Edge Processor

2020 ◽  
Vol 10 (2) ◽  
pp. 19
Author(s):  
Alfio Di Mauro ◽  
Hamed Fatemi ◽  
Jose Pineda de Gyvez ◽  
Luca Benini
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Management Strategy ◽  
Low Cost ◽  
Mode Selection ◽  
Worst Case ◽  
Dynamic Power ◽  
Dynamic Tuning ◽  
Power Management Strategy ◽  
Power Mode

Power management is a crucial concern in micro-controller platforms for the Internet of Things (IoT) edge. Many applications present a variable and difficult to predict workload profile, usually driven by external inputs. The dynamic tuning of power consumption to the application requirements is indeed a viable approach to save energy. In this paper, we propose the implementation of a power management strategy for a novel low-cost low-power heterogeneous dual-core SoC for IoT edge fabricated in 28 nm FD-SOI technology. Ss with more complex power management policies implemented on high-end application processors, we propose a power management strategy where the power mode is dynamically selected to ensure user-specified target idleness. We demonstrate that the dynamic power mode selection introduced by our power manager allows achieving more than 43% power consumption reduction with respect to static worst-case power mode selection, without any significant penalty in the performance of a running application.

scholarly journals Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

2018 ◽  
Vol 7 (3.1) ◽  
pp. 34
Author(s):  
Vithyalakshmi. N ◽  
Nagarajan P ◽  
Ashok Kumar.N ◽  
Vinoth. G.S
Keyword(s):  
Energy Dissipation ◽  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
System Size ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Dynamic Power ◽  
Transition Activity

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation. 

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450023
Author(s):  
MOHAMED O. SHAKER ◽  
MAGDY A. BAYOUMI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Power Supply ◽  
Cmos Technology ◽  
Clock Signal ◽  
Switching Activity ◽  
Successive Approximation Register ◽  
Simulation Results ◽  
Data Switching

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

scholarly journals Thrust Allocation With Dynamic Power Consumption Modulation for Diesel-Electric Ships

2015 ◽  
pp. 1-1 ◽  
Author(s):  
Aleksander Veksler ◽  
Tor Arne Johansen ◽  
Roger Skjetne ◽  
Eirik Mathiesen
Keyword(s):  
Power Consumption ◽  
Dynamic Power ◽  
Thrust Allocation
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