High order mode conversion via focused ion beam milled Bragg gratings in silicon-on-insulator waveguides

Author(s):  
D.J. Moss ◽  
V. Ta'eed ◽  
B.J. Eggleton ◽  
D. Freeman ◽  
M. Samoc ◽  
...  
2004 ◽  
Vol 12 (21) ◽  
pp. 5274 ◽  
Author(s):  
V. G. Ta'eed ◽  
D. J. Moss ◽  
B. J. Eggleton ◽  
D. Freeman ◽  
S. Madden ◽  
...  

2020 ◽  
Vol 59 (34) ◽  
pp. 10688
Author(s):  
Xinyi Zhao ◽  
Yunhe Zhao ◽  
Yunqi Liu ◽  
Zuyao Liu ◽  
Chengbo Mou ◽  
...  

2017 ◽  
Vol 42 (18) ◽  
pp. 3686 ◽  
Author(s):  
Kazi Tanvir Ahmmed ◽  
Hau Ping Chan ◽  
Binghui Li

2017 ◽  
Vol 56 (18) ◽  
pp. 5125 ◽  
Author(s):  
Ming-Yang Chen ◽  
Guo-Dong Cao ◽  
Yan-Qun Tong ◽  
Ling Wang

2004 ◽  
Vol 85 (21) ◽  
pp. 4860-4862 ◽  
Author(s):  
D. J. Moss ◽  
V. G. Ta’eed ◽  
B. J. Eggleton ◽  
D. Freeman ◽  
S. Madden ◽  
...  

Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.


Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.


Sign in / Sign up

Export Citation Format

Share Document