Wafer-Level Heterogeneous Integration of GaN HEMTs and Si (100) MOSFETs

2012 ◽  
Vol 33 (2) ◽  
pp. 200-202 ◽  
Author(s):  
Hyung-Seok Lee ◽  
Kevin Ryu ◽  
Min Sun ◽  
Tomas Palacios
Keyword(s):  
Heterogeneous Integration ◽  
Wafer Level ◽  
Gan Hemts

Ultra-High-Density Interconnect Enabled by Hybrid Bonding for Heterogeneous Integration: Interfacial Characteristics

2021 ◽  
Author(s):  
Mei-Chien Lu
Keyword(s):  
Performance Metrics ◽  
High Volume ◽  
Image Sensor ◽  
Structure Design ◽  
High Density ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Bonding Area ◽  
The Impact ◽  
Interfacial Characteristics

Abstract Hybrid bonding has been explored for more than a decade and implemented recently in high volume production at wafer-to-wafer level for image sensor applications to enable high performance chip-stacking architectures with ultra-high-density chip-to-chip interconnect. The feasibility of sub-micron hybrid bond pitch leading to ultra-high-density chip-to-chip interconnect has been demonstrated due to the elimination of solder bridging issues from microbump method. Hybrid bonding has also been actively considered for logic and memory chip-stacking, chiplets, and heterogeneous integration in general but encountering additional challenges for bonding at die-to-wafer or die-to-die level. Overlay precision, throughput, wafer dicing are among the main causes. Widening the process margin against overlay error by designing innovative hybrid bonding pad structure is highly desirable. This work proposes a method to evaluate these hybrid bonding pad structure designs and to assess the potential performance metrics by analyzing interfacial characteristics at design phase. The bonding areas and ratios of copper-copper, copper-dielectric, and dielectric-dielectric are the proposed key parameters. The correlation between bonding area ratios and overlay errors can provide insights on the sensitivity to process margins. Nonetheless, the impact of copper recess or protrusion associated with bonding area ratios are also highlighted. The proposed method is demonstrated by examining and analyzing the hybrid bonding pad structure design concepts from a few cases reported in literatures as examples. Concerns are identified for elaboration in future designs and optimizations.

Heterogeneous Integration on Fan-Out Wafer Level Packaging Platform

2021 ◽  
Author(s):  
Tc Chai ◽  
David Ho ◽  
Sc Chong ◽  
Ps Sharon Lim ◽  
Hy Hsiao ◽  
...  
Keyword(s):  
Heterogeneous Integration ◽  
Wafer Level ◽  
Wafer Level Packaging

The European 3D Heterogeneous Integration Platform (e-BRAINS) - a Particular Focus on Reliability and Low-Temperature Processes for 3D Integrated Sensor Systems

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001847-001884
Author(s):  
Peter Ramm ◽  
Armin Klumpp ◽  
Alan Mathewson ◽  
Kafil M. Razeeb ◽  
Reinhard Pufall
Keyword(s):  
Low Temperature ◽  
Heterogeneous Integration ◽  
Sensor Systems ◽  
Wafer Level ◽  
3D Integration ◽  
Integrated Sensor ◽  
Integration Platform ◽  
Ultrasonic Agitation ◽  
Bonding Technology ◽  
Low Temperature Bonding

The European 3D heterogeneous integration platform has been established by the consortium of the Integrated Project e-BRAINS [1], where technologies of the following relevant main categories of 3D integration are provided to enable future applications of smart sensor systems:3D System-on-Chip Integration - 3D-SOC: TSV technology for stacking of thinned devices or large IC blocks (global level),3D Wafer-Level-Packaging - 3D-WLP: embedding technology with through-polymer vias (TPV) for stacking of thinned ICs on wafer-level (no TSV), and3D System-in-Package - 3D-SIP: 3D stacking of packaged devices or substrates *definitions according to [2] Regarding TSV performance, the applications do not need ultra-high vertical interconnect densities as for 3D stacked Integrated Circuits – 3D-SIC*. Nevertheless, the lateral sizes of the TSVs are preferably minimized to allow for place and route for small “open” IC areas. Smaller TSVs are also preferred in order to reduce thermo-mechanical stress. e-BRAINS' focus is on how heterogeneous integration and sensor device technologies can be combined to bring new performance levels to targeted applications with high market potentials. The consortium, under coordination of Infineon and technical management by Fraunhofer EMFT, is composed of major European system manufacturers (Infineon, Siemens, SensoNor, 3D PLUS, Vermon and IQE), SMEs (DMCE, Magna Diagnostics, SORIN and eesy-ID), the large research institutions CEA Grenoble, Fraunhofer (EMFT Munich & IIS-EAS Dresden), imec, SINTEF, Tyndall and ITE Warsaw, and universities (EPFL Lausanne, TU Chemnitz and TU Graz). Target applications include automotive, ambient living and medical devices, with a specific focus on wireless sensor systems. Concerning the enabling 3D Heterogeneous Integration Platform, the e-BRAINS partners are working close together, where Infineon, Fraunhofer EMFT, imec and SINTEF are focusing mainly on 3D-SOC and 3D-WLP, and the French system manufacturer 3D PLUS and Tyndall on 3D-WLP and 3D-SIP technologies. The focus of this paper is on low-temperature bonding processes for highly reliable 3D integrated sensor systems. One of the key issues for heterogeneous systems production is the impact of 3D processes to the reliability of the product, i.e. the high built-in stresses caused by e.g. the CTE mismatch of complex layer structures (thin Si, ILDs, metals etc.) in combination with elevated bonding temperatures. As consequence, extensive project work was dedicated in the developments of reliable low-temperature bonding processes. Mainly intermetallic compound (IMC) bonding with Cu/Sn metal systems supported by ultrasonic agitation (Fraunhofer EMFT) was successfully introduced in 3D integration technology (see Fig. 2). A copper/tin solid-liquid interdiffusion (SLID) system was investigated using ultrasonic agitation to reduce the assembly temperature below the melting point of tin. Cleaning procedures are important shortly before joining the samples; dry cleaning has best results due to removal of thin oxide layers. Figure 2 shows a cross section of US supported Cu/Sn bonding at 150C. The intermetallic compounds Cu3Sn and Cu6Sn5 as well as pure tin easily can be identified. Due to low temperature assembly the most stable intermetallic compound (IMC) Cu3Sn has a minor share of the metal system. Most importantly there is no gap between top and bottom part of the joint despite the macroscopic assembly temperature is far away from the melting point of tin. But maybe the ultrasonic agitation brings enough energy to the interfaces, so locally melting can occur. In this way robust IMC bonding technology at 150C could be demonstrated with shear forces of 17 MPa and an alignment accuracy of 3 μm, well-suited for 3D integration. Figure 2: Low-temperature IMC bonding technology using ultrasonic agitation (Fraunhofer EMFT) Reliability for SLID contacts is certainly a very challenging objective especially looking for robust solutions in automotive applications. Thermally induced mechanical stress is the main reason for early fails during temperature cycling. Cross sectioned samples were investigated and methods like nanoindentation, Raman spectroscopy, fibDAC, and high local resolution x-ray scattering were applied to measure the intrinsic stresses. It can be shown that low temperature bonding is the right approach to avoid excessive stress cracking the interface or even fracturing the silicon. Also fatigue of metals can be reduced in a range that plastic deformation is no lifetime limiting factor.

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

2018 ◽  
Vol 15 (4) ◽  
pp. 148-162 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Wafer Level ◽  
Molding Compound ◽  
Shock Test ◽  
Cycling Test

Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a six-layer PCB. The sample sizes for the thermal cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

Packaging without the Package - A More Holistic Moore's Law

2017 ◽  
Vol 2017 (S1) ◽  
pp. 1-40
Author(s):  
Subramanian S. Iyer (Subu)
Keyword(s):  
System Integration ◽  
System Level ◽  
Heterogeneous Integration ◽  
Power Performance ◽  
Wafer Level ◽  
Innovative Materials ◽  
Barrier To Entry ◽  
On Chip ◽  
Market Consolidation ◽  
Conventional Systems

Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. However, as SoCs have become bigger and more complex, the Non-Recurring Engineering (NRE) Charge and time to market have both ballooned out of control leading to ever increasing market consolidation. We need to address this problem through novel methods of system Integration. With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). We will describe the technology we use and the results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems. We extend these concepts to flexible and biocompatible electronics.

scholarly journals Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 342 ◽  
Author(s):  
Tanja Braun ◽  
Karl-Friedrich Becker ◽  
Ole Hoelck ◽  
Steve Voges ◽  
Ruben Kahle ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Form Factors ◽  
Heterogeneous Integration ◽  
Passive Component ◽  
Wafer Level ◽  
Large Area ◽  
Component Integration ◽  
Application Specific Integrated Circuit ◽  
Power Management Unit

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

Asymmetric Wafer-Level Polyimide and Cu/Sn Hybrid Bonding for 3-D Heterogeneous Integration

2019 ◽  
Vol 66 (7) ◽  
pp. 3073-3079 ◽  
Author(s):  
Cheng-Hsien Lu ◽  
Shu-Yan Jhu ◽  
Chiao-Pei Chen ◽  
Bin-Ling Tsai ◽  
Kuan-Neng Chen
Keyword(s):  
Heterogeneous Integration ◽  
Wafer Level
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