Variations of $V_{t}$ Retention Loss in a SONOS Flash Memory Due to a Current-Path Percolation Effect

2011 ◽  
Vol 32 (4) ◽  
pp. 458-460 ◽  
Author(s):  
Y. L. Chou ◽  
Y. T. Chung ◽  
Tahui Wang ◽  
S. H. Ku ◽  
N. K. Zou ◽  
...  
Keyword(s):  
Flash Memory ◽  
Retention Loss ◽  
Current Path ◽  
Percolation Effect ◽  
A Current

Critical Current of Bi-2212 Single Crystal by Doping Oxides as a Pinning Center

2014 ◽  
Vol 95 ◽  
pp. 175-180
Author(s):  
Takuya Agou ◽  
Hiroya Imao
Keyword(s):  
Rare Earth ◽  
Single Crystal ◽  
Single Crystals ◽  
Crystal Surface ◽  
Rare Earth Oxides ◽  
Pinning Centers ◽  
Current Path ◽  
Pinning Center ◽  
Superconducting Current ◽  
A Current

It is necessary to formpinning centers in superconductors to allow the flow of large currents throughthe specimens. To clarify the properties of pinning centers, it is preferableto investigate single crystals. In this study, heat treatment was used to dopevarious oxides into Bi2Sr2CaCu2Ox(Bi-2212) single crystals prepared by self-flux methods and the criticalcurrent (Ic) was measured. The oxides used in this study were Al2O3and the rare earth oxides Er2O3and Nd2O3. At 77K, Nd2O3and Er2O3 are magnetic, whereas Al2O3is nonmagnetic. The Ic of the samples were measured as a current per width of 1cm (Ics). The resulting Ics of the Bi-2212 single crystal was 2.8A/cm and thatof the Al2O3 doped Bi-2212 sample was 4.5A/cm. Comparedwith these samples, doping the other rare earth oxides gave Ics values inexcess 10A/cm. The results indicated that the doping oxides were effective inoperating as pinning centers in the samples. We assumed the current path in asingle crystal, and calculated the Ics by superconducting current simulation.The results indicated that the oxides permeated from a crystal surface in aporous shape. The oxides increase the current which flow in the Cu-O2planes that are parallel to the a-b plane.

Charge Retention Loss in a $\hbox{HfO}_{2}$ Dot Flash Memory via Thermally Assisted Tunneling

2008 ◽  
Vol 29 (1) ◽  
pp. 109-110 ◽  
Author(s):  
Tahui Wang ◽  
H. C. Ma ◽  
C. H. Li ◽  
Y. H. Lin ◽  
C. H. Chien ◽  
...  
Keyword(s):  
Flash Memory ◽  
Charge Retention ◽  
Retention Loss ◽  
Assisted Tunneling

scholarly journals $V_{t}$ Retention Distribution Tail in a Multitime-Program MLC SONOS Memory Due to a Random-Program-Charge-Induced Current-Path Percolation Effect

2012 ◽  
Vol 59 (5) ◽  
pp. 1371-1376 ◽  
Author(s):  
Yueh-Ting Chung ◽  
Tzu-I Huang ◽  
Chi-Wei Li ◽  
You-Liang Chou ◽  
Jung-Piao Chiu ◽  
...  
Keyword(s):  
Induced Current ◽  
Current Path ◽  
Percolation Effect ◽  
Distribution Tail ◽  
Random Program

scholarly journals Design and Implementation of Next Generation Automotive Theft Preventive System

2018 ◽  
Vol 9 (1) ◽  
pp. 118
Author(s):  
K. Hema ◽  
Muralidharan Muralidharan
Keyword(s):  
Low Power ◽  
Flash Memory ◽  
Next Generation ◽  
Auto Theft ◽  
Ultra Low Power ◽  
Design And Implementation ◽  
Prevention System ◽  
Vehicle Security ◽  
Run Up ◽  
A Current

<span lang="EN-IN">In this paper, we proposed to design a next-generation auto theft prevention system by adding significant enhancements and modernizing the existing security features</span><span lang="EN-IN">. </span><span lang="EN-IN">As vehicles turn out to be more refined, vehicle security frameworks must be more grounded than at any other time. A current vehicle uses remote keyless passage framework and Immobilizer framework as the primary weaponry against vehicle robbery. These structures avoid unapproved access of the vehicle to a particular degree, however, are not a secure one. Because of the straightforward and imperfect nature of these security frameworks, auto burglary occurrences worldwide are on the ascent. This venture needs a low power microcontroller however with elite prerequisites. LPC11C14 from NXP Semiconductors addresses these issues and in this manner picked as the primary MCU. It is an ultra-low-power ARM Cortex-M0 based microcontroller that can run up to 50MHz. It has 32KB of Flash memory and 8KB RAM. </span>

scholarly journals A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

Coatings ◽  
2019 ◽  
Vol 9 (8) ◽  
pp. 514 ◽  
Author(s):  
Feng-Tso Chien ◽  
Kuang-Po Hsueh ◽  
Zhen-Jie Hong ◽  
Kuan-Ting Lin ◽  
Yao-Tsung Tsai ◽  
...  
Keyword(s):  
Thin Film ◽  
Electric Field ◽  
Impact Ionization ◽  
Thin Film Transistor ◽  
Ionization Rate ◽  
Field Plate ◽  
Current Path ◽  
Plate Design ◽  
Impact Ionization Rate ◽  
A Current

In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field plate design can allure the electron and alter the electron current path to evade the high electric field area and therefore reduce the device IIR and suppress the kink effect. A two-dimensional device simulator was applied to describe and compare the current path, electric field magnitude distributions, and IIR of the proposed structure and conventional devices. In addition, the advantages of a partial thicker channel RSD design are present, and the leakage current of CES-thin-film transistor (TFT) can be reduced and the ON/OFF current ratio be improved, owing to a smaller drain electric field.

scholarly journals Snapback-Free Reverse-Conducting SOI LIGBT with an Integrated Self-Biased MOSFET

2021 ◽  
Author(s):  
Kemeng Yang ◽  
Jie Wei ◽  
Kaiwei Dai ◽  
Zhen Ma ◽  
Congcong Li ◽  
...  
Keyword(s):  
Power Loss ◽  
Voltage Drop ◽  
Dynamic Performance ◽  
Reverse Current ◽  
Turn On ◽  
Current Path ◽  
Anode Electrode ◽  
Recovery Characteristic ◽  
A Current ◽  
Electron Extraction

Abstract A novel snapback-free RC-LIGBT with integrated self-biased N-MOSFET is proposed and investigated by simulation. The device features an integrated self-biased N-MOSFET(ISM) on the anode active region. One side of the ISM is shorted to the P+ anode electrode of RC-LIGBT and the other side is connected to the N+ anode via a floating ohmic contact. The adaptively turn-on/off of the ISM contributes to improve the static and dynamic performance of the ISM RC-LIGBT. In the forward-state, due to the off-state of the ISM, the snapback could be effectively suppressed without requiring extra device area compared with the SSA (separated shorted anode) and STA (segmented trenches in the anode) LIGBTs. In the reverse conduction, the ISM is turned on and the parasitic NPN in the ISM is punched through, which provides a current path for the reverse current. Meanwhile, during the turn-off and reverse recovery states, the ISM turns on, providing a rapid electron extraction path. Thus, a superior tradeoff between the on-state voltage drop (Von) and turnoff loss (Eoff) as well as an improved reverse recovery characteristic can be obtained. Compared with the STA device, the proposed ISM RC-LIGBT reduces Eoff by 21.5% without snapback. Its reverse recovery charge is reduced by 53.7%/58.6% compared to that of the SSA LIGBT with Lb=40/60μm at the same Von. Due to the prominent static and dynamic characteristic, the power loss of ISM RC-LIGBT in a completed switching cycle is reduced.

Magnetic Field Imaging for 3D applications

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001937-001965
Author(s):  
Jan Gaudestad ◽  
Antonio Orozco
Keyword(s):  
Magnetic Field ◽  
Field Distribution ◽  
Quantum Interference ◽  
Device Fabrication ◽  
Fault Isolation ◽  
Current Path ◽  
Magnetic Field Imaging ◽  
The Magnetic Field ◽  
Field Imaging ◽  
A Current

The challenges that 3D integration present to Failure Analysis require the development of new Fault Isolation techniques that allows for non-destructive, true 3D failure localization. By injecting a current in the device under test (DUT), the current generates a magnetic field around it and this magnetic field is detected by a sensor above the device. Magnetic field imaging (MFI) is a natural candidate for 3D Fault Isolation of complex 3D interconnected devices. This is because the magnetic field generated by the currents in the DUT passes unaffected through all materials used in device fabrication; the presence of multiple metal layers, dies or other opaque layers do not have any impact on the magnetic field signal. The limitations of the technique are not affected by the number of layers in the stacked devise in samples such as wirebonded stacked memory, Through Silicon Via (TSV) stacked die or even package on package (PoP). The sample is raster scanned and magnetic field is acquired at determined steps providing a magnetic image of the field distribution. This magnetic field data is typically processed using a standard inversion technique to obtain a current density map of the device. The resulting current map can then be compared to a circuit diagram, an optical or infrared image, or a non-failing part to determine the fault location. Today, giant-magnetoresistive (GMR) sensors have been added to the Superconducting Quantum Interference Device (SQUID) sensor to allow higher resolution and Fault Isolation (FI) I at die level. Magnetic Field Imaging (MFI), using SQUID as the high sensitive magnetic sensor in combination with a high resolution GMR sensor. A solver algorithm capable of successfully reconstructing a 3D current path based on an acquired magnetic field image from both sensors has been developed. The generic 3D inverse problem has no unique solution. Given a particular 3D magnetic field distribution, there are an infinite number of current path distributions that will result in such magnetic field. This ill-posed problem has restricted, so far, the use of magnetic imaging to 2D. A different kind of 3D solver can be constructed, nevertheless capable of obtaining a single solution. The 3D solver algorithm is not only capable of extracting the 3D current path, but it also provides valuable geometrical information about the device. Accurately being able to position each current segment in a layer allows the FA engineer to follow the current as it vertically moves from one die (or layer) to another. [1,2,3]

scholarly journals Ohmic Contact Mechanism for Ni/C-Faced 4H-n-SiC Substrate

2019 ◽  
Vol 2019 ◽  
pp. 1-5
Author(s):  
Seongjun Kim ◽  
Hong-Ki Kim ◽  
Minwho Lim ◽  
Seonghoon Jeong ◽  
Min-Jae Kang ◽  
...  
Keyword(s):  
Ohmic Contact ◽  
Ohmic Contacts ◽  
Annealed Sample ◽  
Contact Interface ◽  
Ohmic Behavior ◽  
Current Path ◽  
Horizontal Type ◽  
Nisi Phase ◽  
Contact Mechanism ◽  
A Current

In this work, the ohmic contact mechanism of Ni electrodes on C-faced 4H-n-SiC was investigated by evaluating the electrical and microstructural properties in the contact interface as a function of annealing temperatures ranging from 950 to 1100°C. We determined that Ni-silicide, especially the NiSi phase, plays a key role in the formation of ohmic contacts rather than an increase in carbon vacancies in the C-faced SiC substrate. A vertically oriented NiSi phase was observed in the thermally annealed sample at the optimized temperature that behaves as a current path. A further increase in annealing temperature leads to the degradation of ohmic behavior due to the formation of horizontal-type NiSi in the Ni-rich Ni-silicide/NiSi/SiC structure.

Sign in / Sign up

Export Citation Format

Share Document