High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

2006 ◽  
Vol 27 (5) ◽  
pp. 383-386 ◽  
Author(s):  
N. Singh ◽  
A. Agarwal ◽  
L.K. Bera ◽  
T.Y. Liow ◽  
R. Yang ◽  
...  
Keyword(s):  
High Performance ◽  
Silicon Nanowire ◽  
Nanowire Diameter ◽  
Fully Depleted

scholarly journals Decoupling electron and phonon transport in single-nanowire hybrid materials for high-performance thermoelectrics

2021 ◽  
Vol 7 (20) ◽  
pp. eabe6000
Author(s):  
Lin Yang ◽  
Madeleine P. Gordon ◽  
Akanksha K. Menon ◽  
Alexandra Bruefach ◽  
Kyle Haas ◽  
...  
Keyword(s):  
Thermal Conductivity ◽  
Thermal Transport ◽  
Electrical Transport ◽  
High Performance ◽  
Figure Of Merit ◽  
Phonon Transport ◽  
Core Shell ◽  
Nanowire Diameter ◽  
High Performing ◽  
Polycrystalline Thin Films

Organic-inorganic hybrids have recently emerged as a class of high-performing thermoelectric materials that are lightweight and mechanically flexible. However, the fundamental electrical and thermal transport in these materials has remained elusive due to the heterogeneity of bulk, polycrystalline, thin films reported thus far. Here, we systematically investigate a model hybrid comprising a single core/shell nanowire of Te-PEDOT:PSS. We show that as the nanowire diameter is reduced, the electrical conductivity increases and the thermal conductivity decreases, while the Seebeck coefficient remains nearly constant—this collectively results in a figure of merit, ZT, of 0.54 at 400 K. The origin of the decoupling of charge and heat transport lies in the fact that electrical transport occurs through the organic shell, while thermal transport is driven by the inorganic core. This study establishes design principles for high-performing thermoelectrics that leverage the unique interactions occurring at the interfaces of hybrid nanowires.

Simulation and Design of a Silicon Nanowire based Phase Change Memory Cell

2012 ◽  
Vol 1431 ◽  
Author(s):  
Ramin Banan Sadeghian ◽  
Yusuf Leblebici ◽  
Ali Shakouri
Keyword(s):  
Phase Change ◽  
High Speed ◽  
Low Cost ◽  
Silicon Nanowire ◽  
Phase Change Memory ◽  
Random Access ◽  
Memory Cell ◽  
Oxide Thickness ◽  
Nanowire Diameter ◽  
Change Memory

ABSTRACTIn this work we present preliminary calculations and simulations to demonstrate feasibility of programming a nanoscale Phase Change Random Access Memory (PCRAM) cell by means of a silicon nanowire ballistic transistor (SNWBT). Memory cells based on ballistic transistors bear the advantage of having a small size and high-speed operation with low power requirements. A one-dimensional MOSFET model (FETToy) was used to estimate the output current of the nanowire as a function of its diameter. The gate oxide thickness was 1.5 nm, and the Fermi level at source was set to -0.32 eV. For the case of VDS = VGS = 1 V, when the nanowire diameter was increased from 1 to 60 nm, the output power density dropped from 109 to 106 W cm-2 , while the current increased from 20 to 90 μA. Finite element electro-thermal analysis were carried out on a segmented cylindrical phase-change memory cell made of Ge2Sb2Te5 (GST) chalcogenide, connected in series to the SNWBT. The diameter of the combined device, d, and the aspect ratio of the GST region were selected so as to achieve optimum heating of the GST. With the assumption that the bulk thermal conductivity of GST does not change significantly at the nanoscale, it was shown that for d = 24 nm, a ‘reset’ programming current of ID = 80 μA can heat the GST up to its melting point. The results presented herein can help in the design of low cost, high speed, and radiation tolerant nanoscale PCRAM devices.

NAND And NOR Logic-In-Memory Comprising Silicon Nanowire Feedback Field-Effect Transistors

2021 ◽  
Author(s):  
Yejin Yang ◽  
Juhee Jeon ◽  
Jaemin Son ◽  
Kyoungah Cho ◽  
Sangsig Kim
Keyword(s):  
Processing Speed ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Logic Gate ◽  
High Energy ◽  
Zero Bias ◽  
Computing Systems ◽  
Data Movement

Abstract The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations. Here, we present a NAND and NOR LIM composed of silicon nanowidre feedback field-effect transistors, whose configuration resembles that of CMOS logic gate circuits. The LIM can perform memory operations to retain its output logic under zero-bias conditions as well as logic operations with a high processing speed of nanoseconds. The newly proposed dynamic voltage-transfer characteristics verify the operating principle of the LIM. This study demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues.

scholarly journals High Performance GAA SNWT with a Triangular Cross Section: Simulation and Experiments

2018 ◽  
Vol 8 (9) ◽  
pp. 1553 ◽  
Author(s):  
Ming Li ◽  
Gong Chen ◽  
Ru Huang
Keyword(s):  
Cross Section ◽  
High Performance ◽  
Silicon Nanowire ◽  
Wet Etching ◽  
Excellent Performance ◽  
Cross Sectional ◽  
Triangular Cross Section ◽  
Tcad Simulation ◽  
Equivalent Distance ◽  
20 Nm

In this paper, we present a gate-all-around silicon nanowire transistor (GAA SNWT) with a triangular cross section by simulation and experiments. Through the TCAD simulation, it was found that with the same nanowire width, the triangular cross-sectional SNWT was superior to the circular or quadrate one in terms of the subthreshold swing, on/off ratio, and SCE immunity, which resulted from the smallest equivalent distance from the nanowire center to the surface in triangular SNWTs. Following this, we fabricated triangular cross-sectional GAA SNWTs with a nanowire width down to 20 nm by TMAH wet etching. This process featured its self-stopped etching behavior on a silicon (1 1 1) crystal plane, which made the triangular cross section smooth and controllable. The fabricated triangular SNWT showed an excellent performance with a large Ion/Ioff ratio (~107), low SS (85 mV/dec), and preferable DIBL (63 mV/V). Finally, the surface roughness mobility of the fabricated device at a low temperature was also extracted to confirm the benefit of a stable cross section.

Planar fully depleted SOI technology: The convergence of high performance and low power towards multimedia mobile applications

2012 ◽  
Author(s):  
Bertrand Pelloux-Prayer ◽  
Milovan Blagojevic ◽  
Olivier Thomas ◽  
Amara Amara ◽  
Andrei Vladimirescu ◽  
...  
Keyword(s):  
Low Power ◽  
Mobile Applications ◽  
High Performance ◽  
Fully Depleted ◽  
Soi Technology

High performance horizontal gate-all-around silicon nanowire field-effect transistors

2012 ◽  
Vol 23 (39) ◽  
pp. 395202 ◽  
Author(s):  
O Shirak ◽  
O Shtempluck ◽  
V Kotchtakov ◽  
G Bahir ◽  
Y E Yaish
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Silicon Nanowire

Realization of high performance silicon nanowire based solar cells with large size

2013 ◽  
Vol 24 (23) ◽  
pp. 235402 ◽  
Author(s):  
X X Lin ◽  
X Hua ◽  
Z G Huang ◽  
W Z Shen
Keyword(s):  
Solar Cells ◽  
High Performance ◽  
Silicon Nanowire ◽  
Large Size
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