Corrections to "200-mm Wafer Scale Transfer of 0.18$mu$m Dual-Damascene Cu/SiO$_2$Interconnection System to Plastic Substrates"

2006 ◽  
Vol 27 (3) ◽  
pp. 198-198
Author(s):  
W.H. Teh ◽  
G. Lihui ◽  
R. Kumar ◽  
D.-L. Kwong
Keyword(s):  
Plastic Substrates ◽  
Wafer Scale ◽  
Dual Damascene

Wafer-Scale, Homogeneous MoS2Layers on Plastic Substrates for Flexible Visible-Light Photodetectors

2016 ◽  
Vol 28 (25) ◽  
pp. 5025-5030 ◽  
Author(s):  
Yi Rang Lim ◽  
Wooseok Song ◽  
Jin Kyu Han ◽  
Young Bum Lee ◽  
Sung Jun Kim ◽  
...  
Keyword(s):  
Visible Light ◽  
Plastic Substrates ◽  
Wafer Scale

A Micro Stenciling Process for Wafer Scale Metallization of Plastic Substrates

2001 ◽  
pp. 387-388 ◽  
Author(s):  
Swomitra K. Mohanty ◽  
Mason Graff ◽  
Kumar Ravula ◽  
Arum Han ◽  
A. Bruno Frazier
Keyword(s):  
Plastic Substrates ◽  
Wafer Scale

Wafer scale integration

1988 ◽  
Vol 135 (6) ◽  
pp. 281
Author(s):  
J.B. Butcher ◽  
K.K. Johnstone
Keyword(s):  
Wafer Scale ◽  
Wafer Scale Integration ◽  
Scale Integration

Investigation of Plasma Treatment Conditions for Wafer-Scale Room-Temperature Bonding Using Ultrathin Au Films in Ambient Air

2019 ◽  
Vol 139 (7) ◽  
pp. 217-218
Author(s):  
Michitaka Yamamoto ◽  
Takashi Matsumae ◽  
Yuichi Kurashima ◽  
Hideki Takagi ◽  
Tadatomo Suga ◽  
...  
Keyword(s):  
Plasma Treatment ◽  
Room Temperature ◽  
Ambient Air ◽  
Wafer Scale ◽  
Treatment Conditions

Experimental Characterization of the Reliability of 3-Terminal Dual-Damascene Copper Interconnect Trees

2002 ◽  
Vol 716 ◽  
Author(s):  
C. L. Gan ◽  
C. V. Thompson ◽  
K. L. Pey ◽  
W. K. Choi ◽  
F. Wei ◽  
...  
Keyword(s):  
Stress Conditions ◽  
Experimental Characterization ◽  
Contact Lines ◽  
Tree Structures ◽  
Similar Test ◽  
Dual Damascene ◽  
Copper Interconnect ◽  
Test Conditions

AbstractElectromigration experiments have been carried out on simple Cu dual-damascene interconnect tree structures consisting of straight via-to-via (or contact-to-contact) lines with an extra via in the middle of the line. As with Al-based interconnects, the reliability of a segment in this tree strongly depends on the stress conditions of the connected segment. Beyond this, there are important differences in the results obtained under similar test conditions for Al-based and Cu-based interconnect trees. These differences are thought to be associated with variations in the architectural schemes of the two metallizations. The absence of a conducting electromigrationresistant overlayer in Cu technology, and the possibility of liner rupture at stressed vias lead to significant differences in tree reliabilities in Cu compared to Al.

Dual Damascene Process for FatWires in Copper/FSG Technology

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  
Keyword(s):  
Line Width ◽  
Lower Cost ◽  
Process Window ◽  
Cmos Process ◽  
Dual Damascene ◽  
Damascene Process ◽  
Interconnect Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

Characteristics of Indium Tin Zinc Oxide Thin Film Transistors with Plastic Substrates

2018 ◽  
Vol 28 (4) ◽  
pp. 247-253
Author(s):  
Dae-Gyu Yang ◽  
Hyoung-Do Kim ◽  
Jong-Heon Kim ◽  
Hyun-Suk Kim
Keyword(s):  
Thin Film ◽  
Zinc Oxide ◽  
Thin Film Transistors ◽  
Oxide Thin Film ◽  
Zinc Oxide Thin Film ◽  
Plastic Substrates
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