200 mm wafer-scale substrate transfer of 0.13μmCu∕low-k (Black Diamond™) dual-damascene interconnection to glass substrates

2005 ◽  
Vol 87 (4) ◽  
pp. 043103 ◽  
Author(s):  
W. H. Teh ◽  
R. Kumar ◽  
D. L. Kwong
Keyword(s):  
Wafer Scale ◽  
Glass Substrates ◽  
Dual Damascene ◽  
Low K ◽  
Substrate Transfer

Formation of highly reliable Cu/low-k interconnects by using CVD Co barrier in dual damascene structures

2011 ◽  
Author(s):  
Hye Kyung Jung ◽  
Hyun-Bae Lee ◽  
Matsuda Tsukasa ◽  
Eunji Jung ◽  
Jong-Ho Yun ◽  
...  
Keyword(s):  
Dual Damascene ◽  
Low K

Process-Oriented Stress Modeling and Stress Evolution During Cu/Low-K BEOL Processing

2004 ◽  
Vol 812 ◽  
Author(s):  
Charlie Jun Zhai ◽  
Paul R. Besser ◽  
Frank Feustel
Keyword(s):  
Stress State ◽  
Mechanical Stress ◽  
Plane Stress ◽  
Cmos Technology ◽  
Film Deposition ◽  
Stress Evolution ◽  
Process Step ◽  
Dual Damascene ◽  
Process Oriented ◽  
Low K

AbstractThe damascene fabrication method and the introduction of low-K dielectrics present a host of reliability challenges to Cu interconnects and fundamentally change the mechanical stress state of Cu lines. In order to capture the effect of individual process steps on the stress evolution in the BEoL (Back End of Line), a process-oriented finite element modeling (FEM) approach was developed. In this model, the complete stress history at any step of BEoL can be simulated as a dual damascene Cu structure is fabricated. The inputs to the model include the temperature profile during each process step and materials constants. The modeling results are verified in two ways: through wafer-curvature measurement during multiple film deposition processes and with X-Ray diffraction to measure the mechanical stress state of the Cu interconnect lines fabricated using 0.13um CMOS technology. The Cu line stress evolution is simulated during the process of multi-step processing for a dual damascene Cu/low-K structure. It is shown that the in-plane stress of Cu lines is nearly independent of subsequent processes, while the out-of-plane stress increases considerably with the subsequent process steps.

Mechanical Stress Influence on Electronic Transport in Low-$k$ SiOC Dielectric Dual Damascene Capacitor

2013 ◽  
Vol 34 (8) ◽  
pp. 1056-1058 ◽  
Author(s):  
Ya-Liang Yang ◽  
Tai-Fa Young ◽  
Ting-Chang Chang ◽  
Jia-Haw Hsu ◽  
Tsung-Ming Tsai ◽  
...  
Keyword(s):  
Mechanical Stress ◽  
Electronic Transport ◽  
Dual Damascene ◽  
Low K ◽  
Stress Influence
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