Nahalal: Cache Organization for Chip Multiprocessors

Zvika Guz; Idit Keidar; Avinoam Kolodny; Uri Weiser

doi:10.1109/l-ca.2007.6

Nahalal: Cache Organization for Chip Multiprocessors

IEEE Computer Architecture Letters ◽

10.1109/l-ca.2007.6 ◽

2007 ◽

Vol 6 (1) ◽

pp. 21-24 ◽

Cited By ~ 12

Author(s):

Zvika Guz ◽

Idit Keidar ◽

Avinoam Kolodny ◽

Uri Weiser

Keyword(s):

Chip Multiprocessors ◽

Cache Organization

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Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors

IEEE Transactions on Parallel and Distributed Systems ◽

10.1109/tpds.2011.238 ◽

2012 ◽

Vol 23 (6) ◽

pp. 1038-1046 ◽

Cited By ~ 9

Author(s):

A. Abousamra ◽

A. K. Jones ◽

R. Melhem

Keyword(s):

Chip Multiprocessors ◽

Access Latency ◽

Cache Organization

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A study on optimally co-scheduling jobs of different lengths on chip multiprocessors

Proceedings of the 6th ACM conference on Computing frontiers - CF '09 ◽

10.1145/1531743.1531752 ◽

2009 ◽

Cited By ~ 23

Author(s):

Kai Tian ◽

Yunlian Jiang ◽

Xipeng Shen

Keyword(s):

Chip Multiprocessors ◽

On Chip

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Fast synchronization for chip multiprocessors

ACM SIGARCH Computer Architecture News ◽

10.1145/1105734.1105743 ◽

2005 ◽

Vol 33 (4) ◽

pp. 64-69 ◽

Cited By ~ 8

Author(s):

Jack Sampson ◽

Rubén González ◽

Jean-Francois Collard ◽

Norman P. Jouppi ◽

Mike Schlansker

Keyword(s):

Chip Multiprocessors

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Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs

ACM SIGPLAN Notices ◽

10.1145/2644865.2541976 ◽

2014 ◽

Vol 49 (4) ◽

pp. 715-728

Author(s):

Woo-Cheol Kwon ◽

Tushar Krishna ◽

Li-Shiuan Peh

Keyword(s):

Single Cycle ◽

Cache Organization

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Embedded RAIDs-on-chip for bus-based chip-multiprocessors

ACM Transactions on Embedded Computing Systems ◽

10.1145/2533316 ◽

2014 ◽

Vol 13 (4) ◽

pp. 1-36 ◽

Cited By ~ 2

Author(s):

Luis Angel D. Bathen ◽

Nikil D. Dutt

Keyword(s):

Chip Multiprocessors ◽

On Chip

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Cache Organization for Embeded Processors: CAM-vs-SRAM

2006 IEEE International SOC Conference ◽

10.1109/socc.2006.283902 ◽

2006 ◽

Cited By ~ 5

Author(s):

Baker Mohammad ◽

Paul Bassett ◽

Jacob Abraham ◽

Adnan Aziz

Keyword(s):

Cache Organization

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Task and Communication Allocation for Real-time Tasks to Networks-on-Chip Multiprocessors

2020 Second International Conference on Embedded & Distributed Systems (EDiS) ◽

10.1109/edis49545.2020.9296446 ◽

2020 ◽

Author(s):

Chawki Benchehida ◽

Mohammed Kamel Benhaoua ◽

Houssam-Eddine Zahaf ◽

Giuseppe Lipari

Keyword(s):

Real Time ◽

Chip Multiprocessors ◽

Networks On Chip ◽

On Chip

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Investigation of LSTM based prediction for dynamic energy management in chip multiprocessors

2017 Eighth International Green and Sustainable Computing Conference (IGSC) ◽

10.1109/igcc.2017.8323597 ◽

2017 ◽

Cited By ~ 2

Author(s):

Milad Ghorbani Moghaddam ◽

Wenkai Guan ◽

Cristinel Ababei

Keyword(s):

Energy Management ◽

Chip Multiprocessors ◽

Dynamic Energy Management

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NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines

2018 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2018.8351128 ◽

2018 ◽

Author(s):

Pooneh Safayenikoo ◽

Arghavan Asad ◽

Mahmood Fathy ◽

Farah Mohammadi

Keyword(s):

Energy Efficient ◽

Chip Multiprocessors ◽

Cache Architecture

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A case for shared instruction cache on chip multiprocessors running OLTP

ACM SIGARCH Computer Architecture News ◽

10.1145/1024295.1024297 ◽

2004 ◽

Vol 32 (3) ◽

pp. 11-18 ◽

Cited By ~ 3

Author(s):

Partha Kundu ◽

Murali Annavaram ◽

Trung Diep ◽

John Shen

Keyword(s):

Chip Multiprocessors ◽

Instruction Cache ◽

On Chip

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