A 4.5-mW Closed-Loop $\Delta\Sigma$ Micro-Gravity CMOS SOI Accelerometer

2006 ◽  
Vol 41 (12) ◽  
pp. 2983-2991 ◽  
Author(s):  
Babak Vakili Amini ◽  
Reza Abdolvand ◽  
Farrokh Ayazi
Keyword(s):  
Closed Loop ◽  
Delta Sigma ◽  
Micro Gravity

A 1–3 GHz Delta–Sigma-Based Closed-Loop Fully Digital Phase Modulator in 45-nm CMOS SOI

2017 ◽  
Vol 52 (5) ◽  
pp. 1185-1195 ◽  
Author(s):  
Hamed Gheidi ◽  
Toshifumi Nakatani ◽  
Vincent W. Leung ◽  
Peter M. Asbeck
Keyword(s):  
Closed Loop ◽  
Phase Modulator ◽  
Digital Phase ◽  
Delta Sigma

RF Input Matching Design for Closed-Loop Direct Delta–Sigma Receivers

2015 ◽  
Vol 63 (4) ◽  
pp. 1370-1379 ◽  
Author(s):  
Kim B. Ostman ◽  
Mikko Englund ◽  
Olli Viitala ◽  
Kari Stadius ◽  
Kimmo Koli ◽  
...  
Keyword(s):  
Closed Loop ◽  
Input Matching ◽  
Delta Sigma ◽  
Matching Design

A 1 V INTEGRATION AND ACCURACY AND POWER IMPROVED HEARING AID SYSTEM WITH THE TRIPLE OSCILLATION-BASED LOOPS TECHNIQUE

2014 ◽  
Vol 23 (04) ◽  
pp. 1450056 ◽  
Author(s):  
FANYANG LI ◽  
TAO YIN ◽  
XIAOYU WANG
Keyword(s):  
Circuit Design ◽  
Closed Loop ◽  
Supply Voltage ◽  
Hearing Aid ◽  
Current Mode ◽  
Cmos Process ◽  
Power Performance ◽  
Dc Offset ◽  
Offset Voltage ◽  
Delta Sigma

We present the integration and accuracy and power improved hearing aid system that proposes the triple oscillation-based loops (TOL) technique. Compared with the conventional techniques, the technique replaces the interface capacitors, A/D and D/A convertors with the oscillation-based closed loop and the calibration/operation feedback paths, which are able to enhance the integration of the system and improve the system's accuracy and power performance. Specifically, the technique achieves the only once of the second-order delta-sigma modulation with an integrator and an oscillator. To realize the architecture, the current mode blocks with calibration and successive subtraction are presented on the circuit design. Simulated with a 0.13 μm standard CMOS process in Cadence, with the 16 ohm loudspeaker impedance under the 1 V supply voltage, the input referred DC offset voltage with interface capacitor free is achieved below 2.5 mV; and the signal-to-noise and distortion rate (SNDR) achieves 50 dB@400 mVp-p output voltage. Moreover, the power consumption with no load is maintained within 350 μW.

Intestinal Bacteriology of Closed Loop, Strangulated Obstruction in Dogs.

1961 ◽  
Vol 41 (3) ◽  
pp. 245-250 ◽  
Author(s):  
George H. Bornside ◽  
Isidore Cohn
Keyword(s):  
Closed Loop
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