scholarly journals An all-digital phase-locked loop for high-speed clock generation

2003 ◽  
Vol 38 (2) ◽  
pp. 347-351 ◽  
Author(s):  
Ching-Che Chung ◽  
Chen-Yi Lee
Keyword(s):  
High Speed ◽  
Phase Locked Loop ◽  
Clock Generation ◽  
Digital Phase

scholarly journals Design of High frequency Voltage Controlled Oscillators for Phase Locked Loop

2018 ◽  
Vol 7 (3.12) ◽  
pp. 871
Author(s):  
Thejusraj. H ◽  
Prithivi Raj ◽  
J Selvakumar ◽  
S Praveen Kumar
Keyword(s):  
Power Consumption ◽  
High Frequency ◽  
High Speed ◽  
Phase Locked Loop ◽  
Clock Recovery ◽  
Ring Oscillator ◽  
Voltage Controlled Oscillator ◽  
Voltage Controlled Oscillators ◽  
Clock Generation ◽  
Consumption Values

This paper presents the analysis of various oscillators that generate high frequency of oscillation for high speed communication, clock generation and clock recovery. The Ring oscillator and the Current Starved Voltage Controlled Oscillator(CSVCO) (for 5-stagewithout resistor and with resistor) have been implemented using the Cadence Virtuoso tool in 90 nm technology. The generated frequency of oscillation and the power consumption values of the voltage controlled oscillators have been calculated after inclusion in the PLL, and were also compared to identify the most suitable voltage controlled oscillator for a given application.

Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

2009 ◽  
Vol 96 (11) ◽  
pp. 1183-1189 ◽  
Author(s):  
S. Moorthi ◽  
D. Meganathan ◽  
D. Janarthanan ◽  
P. Praveen Kumar ◽  
J. Raja Paul Perinbam
Keyword(s):  
High Speed ◽  
Phase Locked Loop ◽  
System On Chip ◽  
Clock Generator ◽  
Digital Phase ◽  
Low Jitter ◽  
On Chip
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