A review of common receive-end adaptive equalization schemes and algorithms for a high-speed serial backplane

Author(s):  
C.E. Berndt ◽  
T. Kwasniewski
Author(s):  
SABITA NAHATA ◽  
SUBRATA BHATTACHARYA

Inter-symbol interference (ISI) due to multipath fading is a vital problem in high-speed wireless communication which restricts communication quality and capacity. Therefore, in addition to choosing a fading mitigation technique, it is also important to strategically select a modulation scheme for effective data transmission. Recent literature review on wireless standards, such as 3G and 4G indicates that QAM and QPSK are suitable choices for data transmission. In this paper, a comparative analysis on selected modulation schemes is performed in a fading environment. The mitigation of fading is done using adaptive equalization technique. Also, we show that the signal to noise ratio (SNR) is an important parameter to choose. It is observed that, even when an adaptive equalizer is used at the receiver, a very low SNR gives very high symbol error rate (SER). We derive some important conclusions from our simulation result: QPSK shows minimum SER, whereas 256-PSK and 256-PAM perform worse. Given its spectral efficiency and a low SER, the best choice is 256- QAM.


Author(s):  
Miaomiao Wu ◽  
Zhengbin Pang ◽  
Fangxu Lv ◽  
Jianjun Shi ◽  
Heming Wang ◽  
...  

2020 ◽  
Vol 460 ◽  
pp. 125022
Author(s):  
Cheng Ju ◽  
Na Liu ◽  
Changhong Li

2018 ◽  
Vol 2018 ◽  
pp. 1-9 ◽  
Author(s):  
Chen Cai ◽  
Jian-zhong Zhao ◽  
Yu-mei Zhou

The equalization of a large attenuation signal and multirate communication in high-speed serial interface is hard to balance. To overcome this difficulty, an adaptive equalization system with optimized eye-opening monitor is proposed. The designed eye-opening monitor is based on the asynchronous statistic eye diagram tracking algorithm, and the eye diagram is obtained by undersampling with the low-speed asynchronous clock. With the eye-opening monitor into the adaptive loop, an adaptive equalization system combined with continuous-time linear equalization (CTLE) is completed. And the inductor peaking technology is used to improve the capacity of compensation. With SMIC 28 nm CMOS process to achieve the overall design, the power consumption and core chip area are 12 mW @ 12.5 Gbps and 0.12 mm2, respectively. And postsimulation results show that it can offer compensation from 6 to 21 dB for 1.25–12.5 Gbps range of receiving data, which achieves a large range of data rate and channel loss, and its power efficiency is 0.046 pJ/bit/dB for the worst case, which is better than most previous works.


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