Effect of Glitches on the Efficiency of Components’ Region-Constrained Placement as a Fast Approach to Reduce FPGA’s Dynamic Power Consumption

2006 ◽  
Author(s):  
S.E. Esmaeili ◽  
N.I. Khachab ◽  
M.Y. Ghannam
Keyword(s):  
Power Consumption ◽  
Dynamic Power ◽  
Fast Approach

scholarly journals Towards an Efficient CNN Inference Architecture Enabling In-Sensor Processing

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 1955
Author(s):  
Md Jubaer Hossain Pantho ◽  
Pankaj Bhowmik ◽  
Christophe Bobda
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Image Sensor ◽  
Machine Learning Algorithms ◽  
Hierarchical Optimization ◽  
Computation Method ◽  
Optimization Approach ◽  
Efficient Computation ◽  
Feature Maps ◽  
Dynamic Power

The astounding development of optical sensing imaging technology, coupled with the impressive improvements in machine learning algorithms, has increased our ability to understand and extract information from scenic events. In most cases, Convolution neural networks (CNNs) are largely adopted to infer knowledge due to their surprising success in automation, surveillance, and many other application domains. However, the convolution operations’ overwhelming computation demand has somewhat limited their use in remote sensing edge devices. In these platforms, real-time processing remains a challenging task due to the tight constraints on resources and power. Here, the transfer and processing of non-relevant image pixels act as a bottleneck on the entire system. It is possible to overcome this bottleneck by exploiting the high bandwidth available at the sensor interface by designing a CNN inference architecture near the sensor. This paper presents an attention-based pixel processing architecture to facilitate the CNN inference near the image sensor. We propose an efficient computation method to reduce the dynamic power by decreasing the overall computation of the convolution operations. The proposed method reduces redundancies by using a hierarchical optimization approach. The approach minimizes power consumption for convolution operations by exploiting the Spatio-temporal redundancies found in the incoming feature maps and performs computations only on selected regions based on their relevance score. The proposed design addresses problems related to the mapping of computations onto an array of processing elements (PEs) and introduces a suitable network structure for communication. The PEs are highly optimized to provide low latency and power for CNN applications. While designing the model, we exploit the concepts of biological vision systems to reduce computation and energy. We prototype the model in a Virtex UltraScale+ FPGA and implement it in Application Specific Integrated Circuit (ASIC) using the TSMC 90nm technology library. The results suggest that the proposed architecture significantly reduces dynamic power consumption and achieves high-speed up surpassing existing embedded processors’ computational capabilities.

scholarly journals Idleness-Aware Dynamic Power Mode Selection on the i.MX 7ULP IoT Edge Processor

2020 ◽  
Vol 10 (2) ◽  
pp. 19
Author(s):  
Alfio Di Mauro ◽  
Hamed Fatemi ◽  
Jose Pineda de Gyvez ◽  
Luca Benini
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Management Strategy ◽  
Low Cost ◽  
Mode Selection ◽  
Worst Case ◽  
Dynamic Power ◽  
Dynamic Tuning ◽  
Power Management Strategy ◽  
Power Mode

Power management is a crucial concern in micro-controller platforms for the Internet of Things (IoT) edge. Many applications present a variable and difficult to predict workload profile, usually driven by external inputs. The dynamic tuning of power consumption to the application requirements is indeed a viable approach to save energy. In this paper, we propose the implementation of a power management strategy for a novel low-cost low-power heterogeneous dual-core SoC for IoT edge fabricated in 28 nm FD-SOI technology. Ss with more complex power management policies implemented on high-end application processors, we propose a power management strategy where the power mode is dynamically selected to ensure user-specified target idleness. We demonstrate that the dynamic power mode selection introduced by our power manager allows achieving more than 43% power consumption reduction with respect to static worst-case power mode selection, without any significant penalty in the performance of a running application.

Subword Switching Activity Minimization to Optimize Dynamic Power Consumption

2009 ◽  
Vol 26 (4) ◽  
pp. 68-77
Author(s):  
M.C. Molina ◽  
R. Ruiz-Sautua ◽  
A. Del Barrio ◽  
J.M. Mendias
Keyword(s):  
Power Consumption ◽  
Switching Activity ◽  
Dynamic Power

scholarly journals Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

2018 ◽  
Vol 7 (3.1) ◽  
pp. 34
Author(s):  
Vithyalakshmi. N ◽  
Nagarajan P ◽  
Ashok Kumar.N ◽  
Vinoth. G.S
Keyword(s):  
Energy Dissipation ◽  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
System Size ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Dynamic Power ◽  
Transition Activity

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation. 

scholarly journals Thrust Allocation With Dynamic Power Consumption Modulation for Diesel-Electric Ships

2015 ◽  
pp. 1-1 ◽  
Author(s):  
Aleksander Veksler ◽  
Tor Arne Johansen ◽  
Roger Skjetne ◽  
Eirik Mathiesen
Keyword(s):  
Power Consumption ◽  
Dynamic Power ◽  
Thrust Allocation

Optimization of Dynamic Power for System on Programmable Chip SOPC

2018 ◽  
pp. 571-600
Author(s):  
Mehdi Jemai ◽  
Siwar Ben Haj Hassine ◽  
Bouraoui Ouni ◽  
Abdellatif Mtibaa
Keyword(s):  
Power Consumption ◽  
Scheduling Algorithm ◽  
Main Idea ◽  
Significant Gain ◽  
Dynamic Power ◽  
System On Programmable Chip

In this chapter, the authors present a new scheduling algorithm that brings a reduction in dynamic power consumption by achieving components scheduling while holding the global latency of the application. The main idea of that algorithm is to augment the latency of some components without impacting the dependency constraint and degrading the global latency of the system. There exist many solutions that manage to increase component's latency; one of them is through decreasing the frequency of their corresponding clocks. Generally, such a method leads to an augmentation in global latency of a system. However, this algorithm manages to reduce the consumed power and hold the same global latency of the system. The presented algorithm has been tested and it provides a significant gain in power at both simulation and physical levels.

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