A 6.7nV/√Hz Sub-mHz-1/f-corner 14b analog-to-digital interface for rail-to-rail precision voltage sensing

2011 ◽  
Author(s):  
Chinwuba D. Ezekwe ◽  
Johan P. Vanderhaegen ◽  
Xinyu Xing ◽  
Ganesh K. Balachandran
Keyword(s):  
Voltage Sensing ◽  
Digital Interface ◽  
Analog To Digital ◽  
Rail To Rail ◽  
Precision Voltage

scholarly journals Iterative Signal Processing for Mitigation of Analog-to-Digital Converter Clipping Distortion in Multiband OFDMA Receivers

2012 ◽  
Vol 2012 ◽  
pp. 1-16 ◽  
Author(s):  
Markus Allén ◽  
Toni Levanen ◽  
Jaakko Marttila ◽  
Mikko Valkama
Keyword(s):  
Fundamental Problem ◽  
Turbo Decoding ◽  
Laboratory Measurements ◽  
Digital Interface ◽  
Analog To Digital ◽  
Front End ◽  
Digital Hardware ◽  
Receiver Performance ◽  
Almost All ◽  
Clipping Distortion

In modern wideband communication receivers, the large input-signal dynamics is a fundamental problem. Unintentional signal clipping occurs, if the receiver front-end with the analog-to-digital interface cannot respond to rapidly varying conditions. This paper discusses digital postprocessing compensation of such unintentional clipping in multiband OFDMA receivers. The proposed method iteratively mitigates the clipping distortion by exploiting the symbol decisions. The performance of the proposed method is illustrated with various computer simulations and also verified by concrete laboratory measurements with commercially available analog-to-digital hardware. It is shown that the clipping compensation algorithm implemented in a turbo decoding OFDM receiver is able to remove almost all the clipping distortion even under significant clipping in fading channel circumstances. That is to say, it is possible to nearly recover the receiver performance to the level, which would be achieved in the equivalent nonclipped situation.

A POWER AND AREA EFFICIENT 65 nm CMOS DELAY-LINE ADC FOR ON-CHIP VOLTAGE SENSING

2013 ◽  
Vol 22 (09) ◽  
pp. 1340014 ◽  
Author(s):  
SIDA AMY SHEN ◽  
SHUANG XIE ◽  
WAI TUNG NG
Keyword(s):  
Power Management ◽  
Delay Line ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Voltage Sensing ◽  
Circuit Performance ◽  
Analog To Digital ◽  
Dynamic Voltage ◽  
On Chip ◽  
Area Efficient

This paper presents a 4-bit windowed delay-line analog-to-digital converter (ADC) implemented in 65 nm CMOS technology for VLSI dynamic voltage scaling power management applications. Good linearity is achieved in the proposed power and area efficient ADC without the use of resistors for compensation. The circuit performance was analyzed theoretically and verified experimentally. The measured DNL is within ±0.25 LSB and INL ±0.15 LSB. It occupies an area of 0.009 mm2. With a sampling rate of 4 MHz, the ADC consumes 14 μW with an ENOB of 4.1 and voltage sensing range from 0.87 V to 1.32 V.

A 10-BIT 0.5 V 100 kS/s SAR ADC WITH A NEW RAIL-TO-RAIL COMPARATOR FOR ENERGY LIMITED APPLICATIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450026 ◽  
Author(s):  
REZA INANLOU ◽  
MOHAMMAD YAVARI
Keyword(s):  
Power Consumption ◽  
Signal To Noise Ratio ◽  
Average Power ◽  
Cmos Process ◽  
Signal To Noise ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Rail To Rail ◽  
Average Power Consumption

In this paper, a 10-bit 0.5 V 100 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a new fully dynamic rail-to-rail comparator is presented. The proposed comparator enhances the input signal range to the rail-to-rail mode, and hence, improves the signal-to-noise ratio (SNR) of the ADC in low supply voltages. The effect of the latch offset voltage is reduced by providing a higher voltage gain in the regenerative latch. To reduce the ADC power consumption further, the binary-weighted capacitive array with an attenuation capacitor (BWA) is employed as the digital-to-analog converter (DAC) in this design. The ADC is designed and simulated in a 90 nm CMOS process with a single 0.5 V power supply. Spectre simulation results show that the average power consumption of the proposed ADC is about 400 nW and the peak signal-to-noise plus distortion ratio (SNDR) is 56 dB. By considering 10% increase in total ADC power consumption due to the parasitics and a loss of 0.22 LSB in ENOB due to the DAC capacitors mismatch, the achieved figure of merit (FoM) is 11.4 fJ/conversion-step.

scholarly journals About the Smart Weather Station

2016 ◽  
Vol 68 (1) ◽  
pp. 26-29
Author(s):  
Mihai Bogdan
Keyword(s):  
Data Sheet ◽  
Smart Sensors ◽  
Smart Sensor ◽  
Weather Station ◽  
Electronic Data ◽  
Digital Interface ◽  
New Approach ◽  
Analog To Digital ◽  
Electrical Signals ◽  
Weather Stations

Abstract Until recently, the Romanian weather stations utilized ordinary transducers that acquire useful information related to the desired physical inputs. These inputs will be converted into electrical signals easy to be processed by analog to digital converters. This paper proposed a new approach based on smart sensors system that change the interior behavior in order to optimize data acquirements from the environment. The smart sensor characteristics are stored into himself in a transducer electronic data sheet form (TEDS). The intelligent transducer generat together with the measured analogic signal also a digital interface. Through this interface the transducer’s catalog data can be read from the transducer.

Analog-to-digital interface system for CCD sensors and cameras

1999 ◽  
Author(s):  
Andrew A. Krasnjuk ◽  
Dmitriy S. Sherhalov ◽  
Vladimir J. Stenin
Keyword(s):  
Digital Interface ◽  
Analog To Digital ◽  
Interface System
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