High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor

Author(s):  
Y. Nitta ◽  
Y. Muramatsu ◽  
K. Amano ◽  
T. Toyama ◽  
J. Yamamoto ◽  
...  
2012 ◽  
Vol 21 (1) ◽  
pp. 7-12
Author(s):  
Sung-Hyun Jo ◽  
Myung-Han Bae ◽  
Joon-Taek Jung ◽  
Pyung Choi ◽  
Jang-Kyoo Shin

2015 ◽  
Vol 15 (8) ◽  
pp. 4365-4372
Author(s):  
Swetha S. George ◽  
Mark F. Bocko ◽  
Zeljko Ignjatovic

Author(s):  
David Sander ◽  
Pavel Stepanov ◽  
Irving N. Weinberg ◽  
Pamela Abshire

2013 ◽  
Vol 58 (10) ◽  
pp. 3359-3375 ◽  
Author(s):  
Hafiz M Zin ◽  
Emma J Harris ◽  
John P F Osmond ◽  
Nigel M Allinson ◽  
Philip M Evans

2007 ◽  
Vol 7 (1) ◽  
pp. 137-150 ◽  
Author(s):  
Michal A. Szelezniak ◽  
Grzegorz W. Deptuch ◽  
Fabrice Guilloux ◽  
Sbastien Heini ◽  
Abdelkader Himmi

2017 ◽  
Vol 2017 ◽  
pp. 1-15 ◽  
Author(s):  
Mostafa Chakir ◽  
Hicham Akhamal ◽  
Hassan Qjidaa

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.


2012 ◽  
Vol 59 (6) ◽  
pp. 1679-1685 ◽  
Author(s):  
Edward H. Lee ◽  
George R. Kunnen ◽  
Alfonso Dominguez ◽  
David R. Allee

2011 ◽  
Vol 81 (2) ◽  
pp. S763-S764
Author(s):  
J.P.F. Osmond ◽  
G. Lupica ◽  
E.J. Harris ◽  
H. Zin ◽  
N.M. Allinson ◽  
...  

2009 ◽  
Vol 80 (10) ◽  
pp. 103704 ◽  
Author(s):  
M. Towrie ◽  
S. W. Botchway ◽  
A. Clark ◽  
E. Freeman ◽  
R. Halsall ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document