Commodity hardware performance in AES processing

2014 ◽  
Author(s):  
Grigore Lupescu ◽  
Laura Gheorghe ◽  
Nicolae Tapus
Keyword(s):  
Commodity Hardware ◽  
Hardware Performance

Hardware Performance Counter-Based Fine-Grained Malware Detection

2020 ◽  
Vol 19 (5) ◽  
pp. 1-17
Author(s):  
Sai Praveen Kadiyala ◽  
Pranav Jadhav ◽  
Siew-Kei Lam ◽  
Thambipillai Srikanthan
Keyword(s):  
Malware Detection ◽  
Performance Counter ◽  
Fine Grained ◽  
Hardware Performance

High rate packet transmission via IP-over-InfiniBand using commodity hardware

2010 ◽  
Author(s):  
Daniela Bortolotti ◽  
Angelo Carbone ◽  
Domenico Galli ◽  
Ignazio Lax ◽  
Umberto Marconi ◽  
...  
Keyword(s):  
Packet Transmission ◽  
High Rate ◽  
Commodity Hardware

Scalable flow probe architecture for 100 Gbps+ rates on commodity hardware: Design Considerations and Approach

2021 ◽  
Author(s):  
Raktim Bhattacharjee ◽  
Rajesh R ◽  
K.R. Prasanna Kumar ◽  
Vinupaul MV ◽  
G. Athithan ◽  
...  
Keyword(s):  
Hardware Design ◽  
Flow Probe ◽  
Commodity Hardware ◽  
Design Considerations

scholarly journals Formal Codesign Methodology with Multistep Partitioning

VLSI Design ◽  
1998 ◽  
Vol 7 (4) ◽  
pp. 401-423 ◽  
Author(s):  
Vincenza Carchiolo ◽  
Michele Malgeri ◽  
Giuseppe Mangioni
Keyword(s):  
Formal Description ◽  
Formal Description Technique ◽  
Trade Off ◽  
Target Architecture ◽  
Design Cycle ◽  
Formal Basis ◽  
Step Algorithm ◽  
Description Technique ◽  
Hardware Performance

A codesign methodology is proposed which is suitable for control-dominated systems but can also be extended to more complex ones. Its main purpose is to optimize the trade-off between hardware performance and software reprogrammability and reconfigurability. The methodology proposed intends to cover the development of the whole system. It deals in greater detail with the steps that can be made without the need for any particular assumption regarding the target architecture. These steps concern splitting up the specification of the system into a set of individually synthesizable elements, and then grouping them for the subsequent mapping stage. In order to decrease the complexity of each partitioning attempt, a two step algorithm is proposed, thus permitting a wide exploration of possible solutions. The methodology is based on the TTL language, an extension of the T-LOTOS Formal Description Technique which provides a large amount of operators as well as a formal basis. Finally, an example pointing out the complete design cycle, excepting the allocation stage is provided.

Using Hardware Performance Counters to support infield GPU Testing

2021 ◽  
Author(s):  
Juan-David Guerrero-Balaguera ◽  
Josie E. Rodriguez Condia ◽  
Matteo Sonza Reorda
Keyword(s):  
Performance Counters ◽  
Hardware Performance Counters ◽  
Hardware Performance
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