FPGA implementation of parallel unitary-rotation Jacobi EVD method based on Network-on-Chip

2013 International Symposium on Intelligent Signal Processing and Communication Systems ◽

10.1109/ispacs.2013.6704512 ◽

2013 ◽

Cited By ~ 2

Author(s):

Chi-Chia Sun ◽

Juergen Goetze

Keyword(s):

Network On Chip ◽

Fpga Implementation ◽

On Chip

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FPGA implementation of network on chip based on Pentacle topology

2011 International Conference on Electronics, Communications and Control (ICECC) ◽

10.1109/icecc.2011.6067664 ◽

2011 ◽

Author(s):

Jian-Xian Zhang ◽

Yin-Tang Yang ◽

Rui Lai ◽

Xiang Gao ◽

Duan Zhou

Keyword(s):

Network On Chip ◽

Fpga Implementation ◽

On Chip

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An Area-Efficient FPGA Implementation of Network-on-Chip (NoC) Router Architecture for Optimized Multicore-SoC Communication

Sensor Letters ◽

10.1166/sl.2018.3985 ◽

2018 ◽

Vol 16 (7) ◽

pp. 552-560 ◽

Cited By ~ 5

Author(s):

R. Poovendran ◽

S. Sumathi

Keyword(s):

Network On Chip ◽

Fpga Implementation ◽

Router Architecture ◽

On Chip ◽

Area Efficient

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An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept

2007 14th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2007.4511160 ◽

2007 ◽

Cited By ~ 2

Author(s):

Karim Hadjiat ◽

Francis St-Pierre ◽

Guy Bois ◽

Yvon Savaria ◽

Michel Langevin ◽

...

Keyword(s):

Network On Chip ◽

Fpga Implementation ◽

Token Ring ◽

On Chip ◽

Scalable Network

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FPGA implementation of network on chip framework using HDL

2010 IEEE Students Technology Symposium (TechSym) ◽

10.1109/techsym.2010.5469219 ◽

2010 ◽

Cited By ~ 4

Author(s):

B C Shubha ◽

P Srikanta

Keyword(s):

Network On Chip ◽

Fpga Implementation ◽

On Chip

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FPGA implementation of low latency routing algorithm for 3D Network on Chip

2011 International Conference on Recent Trends in Information Technology (ICRTIT) ◽

10.1109/icrtit.2011.5972420 ◽

2011 ◽

Cited By ~ 2

Author(s):

A. Vino Vilmet Rose ◽

R. Seshasayanan ◽

G. Oviya

Keyword(s):

Routing Algorithm ◽

Network On Chip ◽

Fpga Implementation ◽

Low Latency ◽

3D Network ◽

On Chip

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FPGA Implementation of Buffer-Less NoC Router for SDM-Based Network-on-Chip

Advances in Intelligent Systems and Computing - Progress in Advanced Computing and Intelligent Engineering ◽

10.1007/978-981-10-6875-1_55 ◽

2017 ◽

pp. 561-567

Author(s):

Y. Amar Babu ◽

G. M. V. Prasad ◽

John Bedford Solomon

Keyword(s):

Network On Chip ◽

Fpga Implementation ◽

On Chip

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Multi-FPGA implementation of a Network-on-Chip based many-core architecture with fast barrier synchronization mechanism

NORCHIP 2010 ◽

10.1109/norchip.2010.5669430 ◽

2010 ◽

Cited By ~ 1

Author(s):

Xiaowen Chen ◽

Shuming Chen ◽

Zhonghai Lu ◽

Axel Jantsch ◽

Bangjian Xu ◽

...

Keyword(s):

Network On Chip ◽

Fpga Implementation ◽

Barrier Synchronization ◽

Synchronization Mechanism ◽

On Chip ◽

Many Core

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FPGA Implementation of Network-on-Chip Router Architecture for Multicore-SoC Communication Paradigm

International Journal of Advance Engineering and Research Development ◽

10.21090/ijaerd.01038 ◽

2014 ◽

Vol 1 (03) ◽

Keyword(s):

Network On Chip ◽

Fpga Implementation ◽

Router Architecture ◽

Communication Paradigm ◽

On Chip

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Real Time Network on Chip (NOC) Architecture with CDMA Techniques with Audio Decoders

Oct. 17-19, 2017 Dubai (UAE) ◽

10.15242/dirpub.dir1017020 ◽

2018 ◽

Keyword(s):

Real Time ◽

Network On Chip ◽

On Chip

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A congestion-aware routing algorithm for simplified mesh-of-tree architecture in network-on-chip designs

Artificial Intelligence and Industrial Application ◽

10.2495/aiia140551 ◽

2015 ◽

Author(s):

J. Fang ◽

L. Yu ◽

Z. Y. Leng

Keyword(s):

Routing Algorithm ◽

Network On Chip ◽

Tree Architecture ◽

On Chip ◽

Congestion Aware

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