Compact model for vertical silicon nanowire based device simulation and circuit design

2015 ◽  
Author(s):  
M. Sharma ◽  
S. Maheshwaram ◽  
Om. Prakash ◽  
A. Bulusu ◽  
A. K. Saxena ◽  
...  
Keyword(s):  
Circuit Design ◽  
Silicon Nanowire ◽  
Device Simulation ◽  
Compact Model

scholarly journals A Review for Compact Model of Thin-Film Transistors (TFTs)

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 599 ◽  
Author(s):  
Nianduan Lu ◽  
Wenfeng Jiang ◽  
Quantan Wu ◽  
Di Geng ◽  
Ling Li ◽  
...  
Keyword(s):  
Thin Film ◽  
Circuit Design ◽  
Surface Potential ◽  
Radio Frequency Identification ◽  
Thin Film Transistors ◽  
Parameter Extraction ◽  
Theoretical Description ◽  
Compact Model ◽  
Compact Models ◽  
Identification Tags

Thin-film transistors (TFTs) have grown into a huge industry due to their broad applications in display, radio-frequency identification tags (RFID), logical calculation, etc. In order to bridge the gap between the fabrication process and the circuit design, compact model plays an indispensable role in the development and application of TFTs. The purpose of this review is to provide a theoretical description of compact models of TFTs with different active layers, such as polysilicon, amorphous silicon, organic and In-Ga-Zn-O (IGZO) semiconductors. Special attention is paid to the surface-potential-based compact models of silicon-based TFTs. With the understanding of both the charge transport characteristics and the requirement of TFTs in organic and IGZO TFTs, we have proposed the surface-potential-based compact models and the parameter extraction techniques. The proposed models can provide accurate circuit-level performance prediction and RFID circuit design, and pass the Gummel symmetry test (GST). Finally; the outlook on the compact models of TFTs is briefly discussed.

BSIM-CMG: Standard FinFET compact model for advanced circuit design

2015 ◽  
Author(s):  
Juan P. Duarte ◽  
Sourabh Khandelwal ◽  
Aditya Medury ◽  
Chenming Hu ◽  
Pragya Kushwaha ◽  
...  
Keyword(s):  
Circuit Design ◽  
Compact Model

scholarly journals Compact modeling of strained GAA SiNW

2019 ◽  
Vol 14 (1) ◽  
pp. 241
Author(s):  
Fatimah K. A Hamid ◽  
N. Ezaila Alias ◽  
R. Ismail ◽  
M. Anas Razali
Keyword(s):  
Threshold Voltage ◽  
Silicon Nanowire ◽  
Current Model ◽  
Drain Current ◽  
Cmos Technology ◽  
Compact Model ◽  
Compact Modeling ◽  
Smoothing Function ◽  
Inversion Charge ◽  
A Charge

<span>Strain-based on advanced MOSFET is a promising candidate for the future of CMOS technology. A numerical model is not favorable compared to a compact model because it cannot be integrated into most simulator software. Thus, a compact model is proposed to overcome the shortcomings in the analytical model. In this paper, a charge-based compact model is presented for long-channel strained Gate-All-Around Silicon Nanowire (GAA SiNW) from an undoped channel to a doped body. The model derivation is based on an inversion charge which has been solved explicitly using the smoothing function. The drain current model is formulated from Pao Sah’s dual integral which is formed in terms of inversion charge at the drain and source terminals. The proposed model has been extensively verified with the numerical simulator data. The strained effect on the electrical parameters are studied based on inversion charge, threshold voltage and current-voltage (I-V) characteristics. Results show that the current, the inversion charge and the threshold voltage can be greatly improved by the strain. The threshold voltage was reduced approximately 40% from the conventional GAA SiNW. Moreover, the inversion charge was improved by 30 % and the on-state current has doubled compared to unstrained device.</span>

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