A CAD approach for on-chip PDN with power and supply noise reduction for multi-voltage SOCS in pre-layout stage

2017 ◽  
Author(s):  
Moumita Chakraborty ◽  
Debasri Saha ◽  
Amlan Chakrabarti
Keyword(s):  
Noise Reduction ◽  
Supply Noise ◽  
On Chip

Decoupling capacitance boosting for on-chip resonant supply noise reduction

2011 ◽  
Author(s):  
Jinmyoung Kim ◽  
Toru Nakura ◽  
Hidehiro Takata ◽  
Koichiro Ishibashi ◽  
Makoto Ikeda ◽  
...  
Keyword(s):  
Noise Reduction ◽  
Supply Noise ◽  
On Chip

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction

2012 ◽  
Vol E95-C (4) ◽  
pp. 643-650 ◽  
Author(s):  
Jinmyoung KIM ◽  
Toru NAKURA ◽  
Hidehiro TAKATA ◽  
Koichiro ISHIBASHI ◽  
Makoto IKEDA ◽  
...  
Keyword(s):  
Noise Reduction ◽  
Supply Noise ◽  
On Chip
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