ScienceGate
Advanced Search
Author Search
Journal Finder
Blog
Sign in / Sign up
ScienceGate
Search
Author Search
Journal Finder
Blog
Sign in / Sign up
Fault-tolerant application specific Network-on-Chip design
2017 7th International Symposium on Embedded Computing and System Design (ISED)
◽
10.1109/ised.2017.8303920
◽
2017
◽
Cited By ~ 2
Author(s):
Parth Shah
◽
Abhishek Kanniganti
◽
J Soumya
Keyword(s):
Fault Tolerant
◽
Network On Chip
◽
Chip Design
◽
On Chip
◽
Application Specific
Download Full-text
Related Documents
Cited By
References
Fault-Tolerant Application-Specific Network-on-Chip Design using Discrete Particle Swarm Optimization
2019 14th Conference on Industrial and Information Systems (ICIIS)
◽
10.1109/iciis47346.2019.9063339
◽
2019
◽
Author(s):
P. Veda Bhanu
◽
J. Soumya
Keyword(s):
Particle Swarm Optimization
◽
Fault Tolerant
◽
Particle Swarm
◽
Network On Chip
◽
Discrete Particle Swarm Optimization
◽
Chip Design
◽
Swarm Optimization
◽
Discrete Particle
◽
On Chip
◽
Application Specific
Download Full-text
A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip
◽
10.1109/vlsisoc.2011.6081674
◽
2011
◽
Author(s):
Zhiliang Qian
◽
Ying Fei Teh
◽
Chi-Ying Tsui
Keyword(s):
Fault Tolerant
◽
Dynamic Reconfiguration
◽
Network On Chip
◽
Chip Design
◽
On Chip
Download Full-text
Application-specific 3D Network-on-Chip design using simulated allocation
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
◽
10.1109/aspdac.2010.5419830
◽
2010
◽
Cited By ~ 4
Author(s):
Pingqiang Zhou
◽
Ping-Hung Yuh
◽
Sachin S. Sapatnekar
Keyword(s):
Network On Chip
◽
Chip Design
◽
3D Network
◽
On Chip
◽
Application Specific
Download Full-text
Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture
Communications in Computer and Information Science - VLSI Design and Test
◽
10.1007/978-981-32-9767-8_37
◽
2019
◽
pp. 442-454
Author(s):
P. Veda Bhanu
◽
Pranav V. Kulkarni
◽
Sai Pranavi Avadhanam
◽
J. Soumya
◽
Linga Reddy Cenkeramaddi
Keyword(s):
Fault Tolerant
◽
Network On Chip
◽
Reconfigurable Architecture
◽
Chip Design
◽
Mesh Topology
◽
On Chip
Download Full-text
Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology
Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08
◽
10.1145/1366110.1366184
◽
2008
◽
Author(s):
Xianfang Tan
◽
Lei Zhang
◽
Shankar Neelkrishnan
◽
Mei Yang
◽
Yingtao Jiang
◽
...
Keyword(s):
Fault Tolerant
◽
Network On Chip
◽
Chip Design
◽
On Chip
Download Full-text
Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization
TENCON 2018 - 2018 IEEE Region 10 Conference
◽
10.1109/tencon.2018.8650346
◽
2018
◽
Author(s):
P. Veda Bhanu
◽
Pranav Kulkarni
◽
Sarthak Jain
◽
Soumya J
◽
Linga Reddy Cenkarmaddi
◽
...
Keyword(s):
Particle Swarm Optimization
◽
Fault Tolerant
◽
Particle Swarm
◽
Network On Chip
◽
Tree Topology
◽
Chip Design
◽
Swarm Optimization
◽
On Chip
Download Full-text
Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement
ACM Journal on Emerging Technologies in Computing Systems
◽
10.1145/3269983
◽
2019
◽
Vol 15
(1)
◽
pp. 1-23
◽
Cited By ~ 1
Author(s):
P. Veda Bhanu
◽
Pranav Venkatesh Kulkarni
◽
Soumya J
Keyword(s):
Fault Tolerant
◽
Network On Chip
◽
Chip Design
◽
On Chip
Download Full-text
Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design
Integration
◽
10.1016/j.vlsi.2017.02.010
◽
2017
◽
Vol 58
◽
pp. 167-188
◽
Cited By ~ 2
Author(s):
Priyajit Mukherjee
◽
Santanu Chattopadhyay
Keyword(s):
Low Power
◽
Network On Chip
◽
Low Latency
◽
Chip Design
◽
On Chip
◽
Path Synthesis
◽
Application Specific
Download Full-text
Voltage island-driven power optimization for application specific network-on-chip design
Proceedings of the great lakes symposium on VLSI - GLSVLSI '12
◽
10.1145/2206781.2206823
◽
2012
◽
Cited By ~ 4
Author(s):
Kan Wang
◽
Sheqin Dong
◽
Satoshi Goto
Keyword(s):
Power Optimization
◽
Network On Chip
◽
Chip Design
◽
On Chip
◽
Application Specific
Download Full-text
Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
◽
10.1109/prime.2018.8430343
◽
2018
◽
Author(s):
P. Veda Bhanu
◽
Pranav Kulkarni
◽
Soumya J.
◽
Linga Reddy Cenkarmaddi
◽
Henning Idsoe
Keyword(s):
Fault Tolerant
◽
Network On Chip
◽
Chip Design
◽
On Chip
Download Full-text
Sign in / Sign up
Close
Export Citation Format
Close
Share Document
Close