Comparative study of single Material gate and Dual Material gate Silicon-On-Insulator Junctionless Transistors

2017 ◽  
Author(s):  
S.C. Wagaj ◽  
Y.V. Chavan
Keyword(s):  
Comparative Study ◽  
Silicon On Insulator ◽  
Junctionless Transistors ◽  
Dual Material ◽  
Single Material

A Comparative Study for the Backside Illumination (BSI) Technology Using Bonding Wafer Cleaning Process for Advanced CMOS Image Sensor

2012 ◽  
Vol 195 ◽  
pp. 75-78
Author(s):  
Chung Kyung Jung ◽  
Sung Wook Joo ◽  
Seoung Hun Jeong ◽  
Sang Wook Ryu ◽  
Han Choon Lee ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Comparative Study ◽  
Quantum Efficiency ◽  
Wafer Bonding ◽  
Image Sensor ◽  
Silicon On Insulator ◽  
Cleaning Process ◽  
Electrochemical Systems ◽  
Wafer Cleaning ◽  
Direct Wafer Bonding

Over the last decades, the concept of backside illumination (BSI) sensors has become one of the leading solutions to optical challenges such as improved quantum efficiency (QE), and cross-talk, respectively [1-. Direct wafer bonding is a method for fabricating advanced substrates for micro-electrochemical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer.

The Microwave Noise Behaviour Of Dual Material Gate Silicon On Insulator

2009 ◽  
Author(s):  
N. Jafar ◽  
N. Soin ◽  
Mohamad Rusop ◽  
Tetsuo Soga
Keyword(s):  
Silicon On Insulator ◽  
Dual Material ◽  
Microwave Noise

STUDY OF DUAL-MATERIAL GATE (DMG) FinFET USING THREE-DIMENSIONAL NUMERICAL SIMULATION

2006 ◽  
Vol 05 (04n05) ◽  
pp. 541-545 ◽  
Author(s):  
DNAYNESH S. HAVALDAR ◽  
AMITAVA DASGUPTA ◽  
NANDITA DASGUPTA
Keyword(s):  
Carrier Transport ◽  
Three Dimensional ◽  
The Novel ◽  
Short Channel Effects ◽  
Short Channel ◽  
Transport Efficiency ◽  
Channel Effects ◽  
Dual Material ◽  
Single Material ◽  
Numerical Simulator

In this work, the novel characteristics of a FinFET with dual-material gate (DMG) are explored theoretically using a 3D numerical simulator and compared with those of a single material gate (SMG) FinFET in terms of threshold voltage roll off, drain induced barrier lowering (DIBL) and the ratio of transconductance (gm) to drain conductance (gd). Our studies show that the DMG structure achieves simultaneous suppression of short channel effects (SCEs), enhancement in carrier transport efficiency and transconductance. Also, these features can be controlled by engineering the work function and length of gate material.

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