Low power high speed switched current comparators for current mode ADC

2007 ◽  
Author(s):  
Yong Sun ◽  
Fengchang Lai
Keyword(s):  
Low Power ◽  
High Speed ◽  
Current Mode ◽  
Switched Current

A LOW POWER AND VARIATION-INSENSITIVE CURRENT-MODE SIGNALING SCHEME

2013 ◽  
Vol 22 (08) ◽  
pp. 1350068
Author(s):  
XINSHENG WANG ◽  
YIZHE HU ◽  
LIANG HAN ◽  
JINGHU LI ◽  
CHENXU WANG ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Current Mode ◽  
Signal Propagation ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Noise Performance ◽  
On Chip ◽  
Variation Tolerance ◽  
Driving Signal

Process and supply variations all have a large influence on current-mode signaling (CMS) circuits, limiting their application on the fields of high-speed low power communication over long on-chip interconnects. A variation-insensitive CMS scheme (CMS-Bias) was offered, employing a particular bias circuit to compensate the effects of variations, and was robust enough against inter-die and intra-die variations. In this paper, we studied in detail the principle of variation tolerance of the CMS circuit and proposed a more suitable bias circuit for it. The CMS-Bias with the proposed bias circuit (CMS-Proposed) can acquire the same variation tolerance but consume less energy, compared with CMS-Bias with the original bias circuit (CMS-Original). Both the CMS schemes were fabricated in 180 nm CMOS technology. Simulation and measured results indicate that the two CMS interconnect circuits have the similar signal propagation delay when driving signal over a 10 mm line, but the CMS-Proposed offers about 9% reduction in energy/bit and 7.2% reduction in energy-delay-product (EDP) over the CMS-Original. Simulation results show that the two CMS schemes only change about 5% in delay when suffering intra-die variations, and have the same robustness against inter-die variations. Both simulation and measurements all show that the proposed bias circuits, employing self-biasing structure, contribute to robustness against supply variations to some extent. Jitter analysis presents the two CMS schemes have the same noise performance.

A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC

2011 ◽  
Vol 20 (01) ◽  
pp. 15-27 ◽  
Author(s):  
XIAN TANG ◽  
KONG PANG PUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
High Speed ◽  
High Accuracy ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Power Efficient ◽  
Successive Approximation Adc ◽  
Switched Current

A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.

A new high speed and low power four-quadrant CMOS analog multiplier in current mode

2009 ◽  
Vol 63 (9) ◽  
pp. 769-775 ◽  
Author(s):  
Ali Naderi ◽  
Abdollah Khoei ◽  
Khayrollah Hadidi ◽  
Hadi Ghasemzadeh
Keyword(s):  
Low Power ◽  
High Speed ◽  
Current Mode ◽  
Analog Multiplier ◽  
Four Quadrant
Sign in / Sign up

Export Citation Format

Share Document