Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology

2012 ◽  
Author(s):  
Li-Wei Chu ◽  
Chun-Yu Lin ◽  
Shiang-Yu Tsai ◽  
Ming-Dou Ker ◽  
Ming-Hsiang Song ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Low Loss ◽  
V Band ◽  
Esd Protection ◽  
Rf Applications

scholarly journals Ultra low power and highly linearized LNA for V-band RF applications in 180 nm CMOS technology

2017 ◽  
Vol 14 (5) ◽  
pp. 20170066-20170066 ◽  
Author(s):  
Farooq A. Khaleel ◽  
Mohammed Nadhim Abbas
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
V Band ◽  
Rf Applications

P-45: On-Chip ESD Protection Design for UXGA/HDTV LCoS in 0.35-μm CMOS Technology

2004 ◽  
Vol 35 (1) ◽  
pp. 404
Author(s):  
Ming-Dou Ker ◽  
Shih-Hung Chen ◽  
Tang-Kui Tseng
Keyword(s):  
Cmos Technology ◽  
Esd Protection ◽  
On Chip

scholarly journals Design of a V Band Power Amplifier Using 65 nm CMOS Technology

2013 ◽  
Vol 24 (4) ◽  
pp. 403-409
Author(s):  
Sungah Lee ◽  
Chenglin Cui ◽  
Seong-Kyun Kim ◽  
Byung-Sung Kim
Keyword(s):  
Power Amplifier ◽  
Cmos Technology ◽  
V Band ◽  
Band Power

Cell-Based ESD Diodes with a Zigzag-Shaped Layout to Enhance the ESD Survival Level

2016 ◽  
Vol 26 (02) ◽  
pp. 1750023
Author(s):  
Minoh Son ◽  
Changkun Park
Keyword(s):  
Integrated Circuits ◽  
Cmos Technology ◽  
Thermal Source ◽  
Esd Protection ◽  
A Cell ◽  
Protection Devices ◽  
Layout Technique ◽  
Typical Layout ◽  
Zigzag Shape ◽  
Survival Level

In this study, we propose cell-based diodes which are laid out with a zigzag shape as electrostatic discharge (ESD) protection elements to enhance the ESD survival level of the diodes. Generally, diodes are regarded as simple ESD protection devices in integrated circuits. During ESD events, the P–N junction of the ESD diode acts as a thermal source. In this study, we investigate a distributed layout method which relies on a cell-based ESD diode to prevent an excessive increase in the temperature at the P–N junction. However, although the distributed layout enhances the ESD survival levels of the ESD diode, the required area increases compared that of a typical layout. Thus, we propose a zigzag layout technique for the cell-based diode to reduce the area and obtain a high ESD survival level. To verify the feasibility of the zigzag layout techniques for cell-based diodes, we designed ESD diodes using 110[Formula: see text]nm RF CMOS technology. The experimental results successfully demonstrate the feasibility of the proposed method.

A Low Loss Fully Embedded Stripline Parallel Coupled BPF for Applications using the 60 GHz Band

2011 ◽  
Vol 2011 (CICMT) ◽  
pp. 000050-000053
Author(s):  
Alexander Schulz ◽  
Sven Rentsch ◽  
Lei Xia ◽  
Robert Mueller ◽  
Jens Mueller
Keyword(s):  
Return Loss ◽  
Bandpass Filter ◽  
Coplanar Waveguide ◽  
Center Frequency ◽  
60 Ghz ◽  
Low Loss ◽  
Wireless Applications ◽  
High Data ◽  
V Band ◽  
Waveguide Transmission

This paper presents a low loss fully embedded bandpass filter (BPF) using low temperature co-fired ceramic (LTCC) for multilayer System-in-Package (SiP) and Multi-Chip-Module (MCM) applications, e.g. wireless applications for the unlicensed 60 GHz band. The measured insertion loss was 1.5 dB at the center frequency 58 GHz, and a return loss of less than −10 dB was achieved, including two grounded coplanar waveguide transmission line (CPWg) to stripline transitions. The four layers BPF has a 3 dB bandwidth of about 11 GHz which supplies e.g. broadband and high data rate applications. The whole BPF requires a substrate area of 5.6 × 2.1 × 0.42 mm3 with transitions and a shielding via fence. This BPF suits well for V-band applications in a LTCC package because of the compact dimensions and the good performance.

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