Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-Chip

Author(s):  
Gabriel Marchesan Almeida ◽  
Remi Busseuil ◽  
Everton Alceu Carara ◽  
Nicolas Hebert ◽  
Sameer Varyani ◽  
...  
2020 ◽  
Author(s):  
Sukhmani K Thethi ◽  
Ravi Kumar

Abstract Dynamic frequency scaling (DFS) is one of the most important approaches for on-the-fly power optimization in modern-day processors. Owing to the trend of chip size shrinkage and increasing the complexity of system design, the problem of achieving an efficient DFS depends upon multi-parametric, non-linear optimization. Hence, it becomes extremely important to identify an optimal underclocking frequency on-the-fly, which depends upon numerous parameters that do not share direct relationship amongst each other. This paper proposes a machine learning approach to DFS of a ubiquitous single-core processor. Several performance parameters of the processor were monitored under an application of a number of clocking frequencies. The dataset thus generated was used to train four artificial neural networks (ANNs) viz. generalized regression (GRNN), decision tree classifier, random forest classifier and backpropagation technique. Under changing parametric conditions of the proposed network, the modes were fit to data while running three applications, i.e. 64- and 1024-point fast fourier transform (FFT) and basicmath applications. The performance of all ANNs was found to be promising and good generalization was obtained with all datasets. In the view of optimizing both speed and power of a system, the results indicate towards suitability of trained GRNN for on-chip deployment for implementing DFS.


2015 ◽  
Vol 25 (01) ◽  
pp. 1640005 ◽  
Author(s):  
Hitoshi Oi

Dynamic frequency scaling (DFS) is a feature commonly found in modern processors. It lowers the clock frequency of a core according to the load level and reduces the power consumption. In this paper, we present a case study of tuning DFS parameters on a platform with an AMD Phenom II X6 using the SPECjEnterprise2010 (jEnt10) and SPECjbb2005 (jbb05) as the workload. In jEnt10, a longer sampling period of core utilization (up to 1.5[Formula: see text]s) reduced the power by 6[Formula: see text]Watt at 25% load level. At 50% load level, combining it with an increased threshold level (98%) to switch the clock frequency further reduced the power consumption by up to 10[Formula: see text]Watt. In jbb05, stretching the sampling period was only effective up to 0.5[Formula: see text]s. The maximum reduction was observed at around 60% load level. Raising the threshold level was not effective for jbb05.


2006 ◽  
Vol 41 (9) ◽  
pp. 2077-2082 ◽  
Author(s):  
J.-H. Kim ◽  
Y.-H. Kwak ◽  
M. Kim ◽  
S.-W. Kim ◽  
C. Kim

2006 ◽  
Vol 2 (3) ◽  
pp. 356-364
Author(s):  
A. P. Kakarountas ◽  
N. D. Zervas ◽  
G. Theodoridis ◽  
H. E. Michail ◽  
D. Soudris

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