Low power state-parallel relaxed adaptive Viterbi decoder design and implementation

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1693707 ◽

2006 ◽

Cited By ~ 1

Author(s):

Fei Sun ◽

Tong Zhang

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

Design And Implementation ◽

Decoder Design

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A Low Power VITERBI Decoder Design With Minimum Transition Hybrid Register Exchange Processing For Wireless Applications

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2010.1402 ◽

2010 ◽

Vol 1 (4) ◽

pp. 14-22 ◽

Cited By ~ 1

Author(s):

S.L Haridas ◽

N.K Choudhari

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

Wireless Applications ◽

Decoder Design

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FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ◽

10.1109/tcsi.2004.838266 ◽

2005 ◽

Vol 52 (2) ◽

pp. 350-365 ◽

Cited By ~ 19

Author(s):

Man Guo ◽

M.O. Ahmad ◽

M.N.S. Swamy ◽

Chunyan Wang

Keyword(s):

Low Power ◽

Systolic Array ◽

Viterbi Decoder ◽

Fpga Design ◽

Design And Implementation

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High-Speed Low-Power Viterbi Decoder Design for TCM Decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2011.2111392 ◽

2012 ◽

Vol 20 (4) ◽

pp. 755-759 ◽

Cited By ~ 23

Author(s):

Jinjin He ◽

Huaping Liu ◽

Zhongfeng Wang ◽

Xinming Huang ◽

Kai Zhang

Keyword(s):

Low Power ◽

High Speed ◽

Viterbi Decoder ◽

Decoder Design

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Low power Viterbi decoder design based on reversible logic gates

2017 4th International Conference on Electronics and Communication Systems (ICECS) ◽

10.1109/ecs.2017.8067869 ◽

2017 ◽

Author(s):

K B Naveen ◽

G S Puneeth ◽

M N Sree Rangaraju

Keyword(s):

Low Power ◽

Logic Gates ◽

Reversible Logic ◽

Viterbi Decoder ◽

Decoder Design ◽

Reversible Logic Gates

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An Efficient Low Power Viterbi Decoder Design using T-algorithm

International Journal of Computer Applications ◽

10.5120/13246-0707 ◽

2013 ◽

Vol 76 (5) ◽

pp. 34-39

Author(s):

K. SridharReddy ◽

M. Nagarjuna ◽

H. Shravan Kumar

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

Decoder Design

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Design and Implementation of Low Power High Speed Viterbi Decoder

Procedia Engineering ◽

10.1016/j.proeng.2012.01.834 ◽

2012 ◽

Vol 30 ◽

pp. 61-68 ◽

Cited By ~ 1

Author(s):

K. Cholan

Keyword(s):

Low Power ◽

High Speed ◽

Viterbi Decoder ◽

Design And Implementation

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A low-power Viterbi decoder design for wireless communications applications

Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454) ◽

10.1109/asic.1999.806538 ◽

2003 ◽

Cited By ~ 13

Author(s):

S. Ranpara ◽

Dong Sam Ha

Keyword(s):

Wireless Communications ◽

Low Power ◽

Viterbi Decoder ◽

Decoder Design

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AAC LC Decoder Design Optimization for Low-power Portable DAB Radio

JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY ◽

10.3724/sp.j.1146.2010.01028 ◽

2011 ◽

Vol 33 (5) ◽

pp. 1229-1233 ◽

Cited By ~ 1

Author(s):

Ming-ying Lu ◽

Li-li Zhang ◽

Guo-yu Wang ◽

Hong-sheng Zhang ◽

Liang-wei Li

Keyword(s):

Low Power ◽

Design Optimization ◽

Decoder Design

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Design and Implementation of a Low Power Ternary Content Addressable Memory (TCAM)

2020 International SoC Design Conference (ISOCC) ◽

10.1109/isocc50952.2020.9333092 ◽

2020 ◽

Author(s):

Karthik S ◽

Karthick D ◽

Sanjaya M V ◽

Madhav Rao

Keyword(s):

Low Power ◽

Content Addressable Memory ◽

Design And Implementation ◽

Ternary Content Addressable Memory

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Design and implementation of low-power DCT chip for portable multimedia terminals

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) ◽

10.1109/sips.1998.715771 ◽

2002 ◽

Author(s):

L.-G. Chen ◽

J.-Y. Jiu ◽

H.-C. Chang

Keyword(s):

Low Power ◽

Design And Implementation

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