A model-based hybrid evolutionary algorithm for fast yield-inclusive design space exploration of analog circuits

2006 ◽  
Author(s):  
A. Somani ◽  
P.P. Chakrabarti ◽  
A. Patra
Keyword(s):  
Evolutionary Algorithm ◽  
Analog Circuits ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Inclusive Design ◽  
Hybrid Evolutionary Algorithm ◽  
Model Based

scholarly journals Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

2015 ◽  
Vol 2015 ◽  
pp. 1-20
Author(s):  
Gongyu Wang ◽  
Greg Stitt ◽  
Herman Lam ◽  
Alan George
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Core Level ◽  
Prediction Methods ◽  
Clock Frequency ◽  
Worst Case ◽  
Model Based ◽  
Dsp Applications

Field-programmable gate arrays (FPGAs) provide a promising technology that can improve performance of many high-performance computing and embedded applications. However, unlike software design tools, the relatively immature state of FPGA tools significantly limits productivity and consequently prevents widespread adoption of the technology. For example, the lengthy design-translate-execute (DTE) process often must be iterated to meet the application requirements. Previous works have enabled model-based, design-space exploration to reduce DTE iterations but are limited by a lack of accurate model-based prediction of key design parameters, the most important of which is clock frequency. In this paper, we present a core-level modeling and design (CMD) methodology that enables modeling of FPGA applications at an abstract level and yet produces accurate predictions of parameters such as clock frequency, resource utilization (i.e., area), and latency. We evaluate CMD’s prediction methods using several high-performance DSP applications on various families of FPGAs and show an average clock-frequency prediction error of 3.6%, with a worst-case error of 20.4%, compared to the best of existing high-level prediction methods, 13.9% average error with 48.2% worst-case error. We also demonstrate how such prediction enables accurate design-space exploration without coding in a hardware-description language (HDL), significantly reducing the total design time.

Multi-objective optimization and analysis for the design space exploration of analog circuits and solar cells

2017 ◽  
Vol 62 ◽  
pp. 373-383 ◽  
Author(s):  
Andrea Patanè ◽  
Andrea Santoro ◽  
Piero Conca ◽  
Giovanni Carapezza ◽  
Antonino La Magna ◽  
...  
Keyword(s):  
Solar Cells ◽  
Analog Circuits ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Multi Objective Optimization ◽  
Multi Objective

Computational Design Synthesis: A Model-Based Approach for Complex Systems

2012 ◽  
Author(s):  
Nicolas Albarello ◽  
Jean-Baptiste Welcomme
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Design Rules ◽  
System Architectures ◽  
Architecture Model ◽  
Model Based ◽  
Design Alternatives ◽  
Systems Architectures ◽  
The Impact

The design of systems architectures often involve a combinatorial design-space made of technological and architectural choices. A complete or large exploration of this design space requires the use of a method to generate and evaluate design alternatives. This paper proposes an innovative approach for the design-space exploration of systems architectures. The SAMOA (System Architecture Model-based OptimizAtion) tool associated to the method is also introduced. The method permits to create a large number of various system architectures combining a set of possible components to address given system functions. The method relies on models that are used to represent the problem and the solutions and to evaluate architecture performances. An algorithm first synthesizes design alternatives (a physical architecture associated to a functional allocation) based on the functional architecture of the system, the system interfaces, a library of available components and user-defined design rules. Chains of components are sequentially added to an initially empty architecture until all functions are fulfilled. The design rules permit to guarantee the viability and validity of the chains of components and, consequently, of the generated architectures. The design space exploration is then performed in a smart way through the use of an evolutionary algorithm, the evolution mechanisms of which are specific to system architecting. Evaluation modules permit to assess the performances of alternatives based on the structure of the architecture model and the data embedded in the component models. These performances are used to select the best generated architectures considering constraints and quality metrics. This selection is based on the Pareto-dominance-based NSGA-II algorithm or, alternatively, on an interactive preference-based algorithm. Iterating over this evolution-evaluation-selection process permits to increase the quality of solutions and, thus, to highlight the regions of interest of the design-space which can be used as a base for further manual investigations. By using this method, the system designers have a larger confidence in the optimality of the adopted architecture than using a classical derivative approach as many more solutions are evaluated. Also, the method permits to quickly evaluate the trade-offs between the different considered criteria. Finally, the method can also be used to evaluate the impact of a technology on the system performances not only by a substituting a technology by another but also by adapting the architecture of the system.

scholarly journals On the Area and Energy Scalability of Wireless Network-on-Chip: A Model-Based Benchmarked Design Space Exploration

2015 ◽  
Vol 23 (5) ◽  
pp. 1501-1513 ◽  
Author(s):  
Sergi Abadal ◽  
Mario Iannazzo ◽  
Mario Nemirovsky ◽  
Albert Cabellos-Aparicio ◽  
Heekwan Lee ◽  
...  
Keyword(s):  
Wireless Network ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Network On Chip ◽  
Model Based ◽  
Energy Scalability ◽  
On Chip
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