High performance circuit techniques for dynamic OR gates

A high performance 256K TTL SRAM using 0.8um triple diffused BiCMOS with 3V circuit techniques

10.1109/vlsic.1991.760057 ◽

2005 ◽

Author(s):

I. Young ◽

M. Denham ◽

J. Greason ◽

G. Kaveh ◽

J. Kolousek ◽

...

Keyword(s):

High Performance ◽

Circuit Techniques

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Noise tolerant circuit techniques for high performance feedthrough logic

2012 International Conference on Emerging Trends in Science, Engineering and Technology (INCOSET) ◽

10.1109/incoset.2012.6513932 ◽

2012 ◽

Author(s):

Sauvagya Ranjan Sahoo ◽

Kamala Kanta Mahapatra

Keyword(s):

High Performance ◽

Circuit Techniques ◽

Noise Tolerant

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Circuit techniques for CMOS low-power high-performance multipliers

IEEE Journal of Solid-State Circuits ◽

10.1109/4.540066 ◽

1996 ◽

Vol 31 (10) ◽

pp. 1535-1546 ◽

Cited By ~ 158

Author(s):

I.S. Abu-Khater ◽

A. Bellaouar ◽

M.I. Elmasry

Keyword(s):

Low Power ◽

High Performance ◽

Circuit Techniques

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Efficient FIR Filter Architecture using FPGA

Recent Advances in Computer Science and Communications ◽

10.2174/2213275912666190603115506 ◽

2020 ◽

Vol 13 (1) ◽

pp. 91-98

Author(s):

Ahmed K. Jameil ◽

Yassir A. Ahmed ◽

Saad Albawi

Keyword(s):

Low Power ◽

Communication Systems ◽

High Performance ◽

Finite Impulse Response ◽

Low Complexity ◽

Fir Filter ◽

Fir Filters ◽

Filter Architecture ◽

Circuit Techniques ◽

And Performance

Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

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