High performance CMOS circuit techniques for the G-4 S/390 microprocessor

2002 ◽  
Author(s):  
J. Warnock ◽  
L. Sigal ◽  
B. Curran ◽  
Y. Chan
Keyword(s):  
High Performance ◽  
Cmos Circuit ◽  
Circuit Techniques

A high performance 256K TTL SRAM using 0.8um triple diffused BiCMOS with 3V circuit techniques

2005 ◽  
Author(s):  
I. Young ◽  
M. Denham ◽  
J. Greason ◽  
G. Kaveh ◽  
J. Kolousek ◽  
...  
Keyword(s):  
High Performance ◽  
Circuit Techniques

High performance CMOS circuit design

2020 ◽  
Author(s):  
Neelam Swami ◽  
Bhupen Khatri
Keyword(s):  
Circuit Design ◽  
High Performance ◽  
Cmos Circuit

CMOS circuit techniques for mm-wave communications

2018 ◽  
Author(s):  
Baoyong Chi ◽  
Zheng Song ◽  
Haikun Jia ◽  
Lixue Kuang ◽  
Jianfu Lin ◽  
...  
Keyword(s):  
Cmos Circuit ◽  
Circuit Techniques

Circuit techniques for CMOS low-power high-performance multipliers

1996 ◽  
Vol 31 (10) ◽  
pp. 1535-1546 ◽  
Author(s):  
I.S. Abu-Khater ◽  
A. Bellaouar ◽  
M.I. Elmasry
Keyword(s):  
Low Power ◽  
High Performance ◽  
Circuit Techniques

High Performance Infrared Detectors Compatible with CMOS-circuit Process

2020 ◽  
Author(s):  
Chao Wang ◽  
Ning Li ◽  
Ning Dai ◽  
Wang-zhou Shi ◽  
Gu-jin Hu ◽  
...  
Keyword(s):  
Infrared Detectors ◽  
High Performance ◽  
Cmos Circuit

Efficient FIR Filter Architecture using FPGA

2020 ◽  
Vol 13 (1) ◽  
pp. 91-98
Author(s):  
Ahmed K. Jameil ◽  
Yassir A. Ahmed ◽  
Saad Albawi
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Performance ◽  
Finite Impulse Response ◽  
Low Complexity ◽  
Fir Filter ◽  
Fir Filters ◽  
Filter Architecture ◽  
Circuit Techniques ◽  
And Performance

Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

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