High performance sense amplifier circuit for low power SRAM applications

2004 ◽  
Author(s):  
Hwang-Cherng Chow ◽  
Shu-Hsien Chang
Keyword(s):  
Low Power ◽  
High Performance ◽  
Amplifier Circuit ◽  
Sense Amplifier

High-performance low-power current sense amplifier using a cross-coupled current-mirror configuration

2002 ◽  
Vol 149 (5) ◽  
pp. 308-314 ◽  
Author(s):  
K.-S. Yeo ◽  
W.-L. Goh ◽  
Z.-H. Kong ◽  
Q-X. Zhang ◽  
W.-G. Yeo
Keyword(s):  
Low Power ◽  
High Performance ◽  
Current Mirror ◽  
Sense Amplifier ◽  
Mirror Configuration

An Ultra-Low Power and High Performance Single Ended Sense Amplifier for Low Voltage Flash Memories

2018 ◽  
Vol 14 (1) ◽  
pp. 157-169 ◽  
Author(s):  
W. Steve Ngueya ◽  
Jean-Michel Portal ◽  
Hassen Aziza ◽  
Julien Mellier ◽  
Stephane Ricard
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Voltage ◽  
Flash Memories ◽  
Ultra Low Power ◽  
Sense Amplifier

A New Simulator Based on Multi Core Processor with Improved Sense Amplifier

2015 ◽  
Vol 24 (09) ◽  
pp. 1550141 ◽  
Author(s):  
Erulappan Sakthivel ◽  
Veluchamy Malathi ◽  
Muruganantham Arunraja
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Routing Algorithm ◽  
Main Idea ◽  
Sense Amplifier ◽  
Area Reduction ◽  
Sense Amplifiers ◽  
On Chip ◽  
Multi Core Processor

In recent days, network-on-chip (NoC) researchers focus mainly on the area reduction and low power consumption both in architectural and algorithmic approach. To achieve low power and high performance in NoC architecture, sense amplifiers (SAs) introduced which can consume less power under various traffic conditions. In order to analyze the performance of architectural NoC design before fabrication level, the new simulator is developed based on multi core processor with improved sense amplifier (MCPSA) in this work. The MCPSA simulator provides user, the flexibility of incorporating various traffic configurations and routing algorithm with user reconfigurable option. In addition, the different SA model can be put into the simulation in plug and play manner for evaluation. The NoC case studies are presented to demonstrate the NoC architecture with double tail sense amplifier (DTSA) and modified-DTSA (M-DTSA) design. The performance metric such as delay, data rate and power consumption is evaluated. The main idea of this new simulator is to interface multisim environment (MSE) into a NoC environment for validating any DTSA.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

High-Performance and Low-Power Full Color Reflective LCD for New Applications

2019 ◽  
pp. 1411
Author(s):  
Hiroyuki Hakoi ◽  
Ming Ni ◽  
Junichi Hashimoto ◽  
Takashi Sato ◽  
Shinji Shimada ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Full Color ◽  
New Applications

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

Sign in / Sign up

Export Citation Format

Share Document