scholarly journals Store Buffer Design in First-Level Multibanked Data Caches

2005 ◽  
Author(s):  
E.F. Torres ◽  
P. Ibanez ◽  
V. Vinals ◽  
J.M. Llaberia
Keyword(s):  
Data Caches ◽  
Buffer Design

scholarly journals Store Buffer Design for Multibanked Data Caches

2009 ◽  
Vol 58 (10) ◽  
pp. 1307-1320
Author(s):  
E. Torres ◽  
P. Ibanez ◽  
V. Vinals-Yufera ◽  
J.M. Llaberia
Keyword(s):  
Data Caches ◽  
Buffer Design

scholarly journals Store Buffer Design in First-Level Multibanked Data Caches

2005 ◽  
Vol 33 (2) ◽  
pp. 469-480 ◽  
Author(s):  
E. F. Torres ◽  
P. Ibanez ◽  
V. Vinals ◽  
J. M. Llaberia
Keyword(s):  
Data Caches ◽  
Buffer Design

Low Energy Associative Data Caches for Embedded Systems

2005 ◽  
pp. 513-525
Author(s):  
Dan Nicolaescu ◽  
Alex Veidenbaum ◽  
Alex Nicolau
Keyword(s):  
Embedded Systems ◽  
Low Energy ◽  
Data Caches

scholarly journals NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution

2012 ◽  
Vol 2012 ◽  
pp. 1-12 ◽  
Author(s):  
Kaveh Aasaraai ◽  
Andreas Moshovos
Keyword(s):  
High Efficiency ◽  
Main Memory ◽  
Data Cache ◽  
Improve Performance ◽  
Data Caches ◽  
Content Addressable Memories ◽  
Processor Designs ◽  
Level Parallelism ◽  
Order Execution ◽  
Runahead Execution

Soft processors often use data caches to reduce the gap between processor and main memory speeds. To achieve high efficiency, simple, blocking caches are used. Such caches are not appropriate for processor designs such as Runahead and out-of-order execution that require nonblocking caches to tolerate main memory latencies. Instead, these processors use non-blocking caches to extract memory level parallelism and improve performance. However, conventional non-blocking cache designs are expensive and slow on FPGAs as they use content-addressable memories (CAMs). This work proposes NCOR, an FPGA-friendly non-blocking cache that exploits the key properties of Runahead execution. NCOR does not require CAMs and utilizes smart cache controllers. A 4 KB NCOR operates at 329 MHz on Stratix III FPGAs while it uses only 270 logic elements. A 32 KB NCOR operates at 278 Mhz and uses 269 logic elements.

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