scholarly journals The robust-algorithm approach to fault tolerance on processor arrays: fault models, fault diameter, and basic algorithms

2002 ◽  
Author(s):  
B. Parhami ◽  
Chi-Hsiang Yeh
Keyword(s):  
Fault Tolerance ◽  
Fault Models ◽  
Robust Algorithm ◽  
Processor Arrays ◽  
Fault Diameter

Fault-Tolerant Software

2009 ◽  
pp. 21-52
Author(s):  
Vincenzo De Florio
Keyword(s):  
Fault Tolerance ◽  
Software Engineering ◽  
Fault Tolerant ◽  
Exception Handling ◽  
Fault Models ◽  
Application Layer ◽  
System Models ◽  
Functional Aspects ◽  
Design Choice ◽  
Computer Services

After having described the main characteristics of dependability and fault-tolerance, it is analyzed here in more detail what it means that a program is fault-tolerant and what are the properties expected from a fault-tolerant program. The main objective of this chapter is introducing two sets of design assumptions that shape the way our fault-tolerant software is structured—the system and the fault models. Often misunderstood or underestimated, those models describe • what is expected from the execution environment in order to let our software system function correctly, and • what are the faults that our system is going to consider. Note that a fault-tolerant program shall (try to) tolerate only those faults stated in the fault model, and will be as defenseless against all other faults as any non fault-tolerant program. Together with the system specification, the fault and system models represent the foundation on top of which our computer services are built. It is not surprising that weak foundations often result in failing constructions. What is really surprising is that in so many cases, little or no attention had been given to those important factors in fault-tolerant software engineering. To give an idea of this, three wellknown accidents are described—the Ariane 5 flight 501, Mariner-1 disasters, and the Therac-25 accidents. In each case it is stressed what went wrong, what were the biggest mistakes, and how a careful understanding of fault models and system models would have helped highlighting the path to avoid catastrophic failures that cost considerable amounts of money and even the lives of innocent people. The other important objective of this chapter is introducing the core subject of this book: Software fault-tolerance situated at the level of the application layer. First of all, it is explained why targeting (also) the application layer is not an open option but a mandatory design choice for effective fault-tolerant software engineering. Secondly, given the peculiarities of the application layer, three properties to measure the quality of the methods to achieve fault-tolerant application software are introduced: 1. Separation of design concerns, that is, how good the method is in keeping the functional aspects and the fault-tolerance aspects separated from each other. 2. Syntactical adequacy, namely how versatile the employed method is in including the wider spectrum of fault-tolerance strategies. 3. Adaptability: How good the employed fault-tolerance method is in dealing with the inevitable changes characterizing the system and its run-time environment, including the dynamics of faults that manifest themselves at service time. Finally, this chapter also defines a few fundamental fault-tolerance services, namely watchdog timers, exception handling, transactions, and checkpointingand- rollback.

scholarly journals Dependability Aspects in Configurable Embedded Operating Systems

2020 ◽  
pp. 85-116
Author(s):  
Horst Schirmeier ◽  
Christoph Borchert ◽  
Martin Hoffmann ◽  
Christian Dietrich ◽  
Arthur Martens ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Research Question ◽  
Fault Models ◽  
System Software ◽  
Embedded Os ◽  
Static Approach ◽  
Attack Surface ◽  
Embedded Operating Systems ◽  
General Reliability ◽  
Hardware Faults

AbstractAs all conceptual layers in the software stack depend on the operating system (OS) to reliably provide resource-management services and isolation, it can be considered the “reliable computing base” that must be hardened for correct operation under fault models such as transient hardware faults in the memory hierarchy. In this chapter, we approach the problem of system-software hardening in three complementary scenarios. (1) We address the following research question: Where do the general reliability limits of static system-software stacks lie, if designed from scratch with reliability as a first-class design goal? In order to reduce the proverbial “attack surface” as far as possible, we harness static application knowledge from an AUTOSAR-compliant task set, and protect the whole OS kernel with AN-encoding. This static approach yields an extremely reliable software system, but is constrained to specific application domains. (2) We investigate how reliable a dynamic COTS embedded OS can become if hardened with programming-language and compiler-based fault-tolerance techniques. We show that aspect-oriented programming is an appropriate means to encapsulate generic software-implemented hardware fault tolerance mechanisms that can be application-specifically applied to a selection of OS components. (3) We examine how system-software stacks can survive even more adverse fault models like whole-system outages, using emerging persistent memory (PM) technology as a vehicle for state conservation. Our findings include that software transactional memory facilitates maintaining consistent state within PM and allows fast recovery.

scholarly journals Synthesis of Classical and Non-Classical CMOS Transistor Fault Models Mapped to Gate-Level for Reconfigurable Hardware-Based Fault Injection

2021 ◽  
Author(s):  
Raha Abedi
Keyword(s):  
Fault Tolerance ◽  
Fault Injection ◽  
Cost Effective ◽  
Fault Model ◽  
Reconfigurable Hardware ◽  
Fault Models ◽  
System Complexity ◽  
Synthesis Time ◽  
Cmos Transistor ◽  
Injection Techniques

One of the main goals of fault injection techniques is to evaluate the fault tolerance of a design. To have greater confidence in the fault tolerance of a system, an accurate fault model is essential. While more accurate than gate level, transistor level fault models cannot be synthesized into FPGA chips. Thus, transistor level faults must be mapped to the gate level to obtain both accuracy and synthesizability. Re-synthesizing a large system for fault injection is not cost effective when the number of faults and system complexity are high. Therefore, the system must be divided into partitions to reduce the re-synthesis time as faults are injected only into a portion of the system. However, the module-based partial reconfiguration complexity rises with an increase in the total number of partitions in the system. An unbalanced partitioning methodology is introduced to reduce the total number of partitions in a system while the size of the partitions where faults are to be injected remains small enough to achieve an acceptable re-synthesis time.

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

2015 ◽  
Vol 64 (10) ◽  
pp. 2926-2939 ◽  
Author(s):  
Guiyuan Jiang ◽  
Jigang Wu ◽  
Yajun Ha ◽  
Yi Wang ◽  
Jizhou Sun
Keyword(s):  
Fault Tolerance ◽  
Heuristic Algorithms ◽  
Three Dimensional ◽  
Processor Arrays
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