Leakage current study and relevant fault localization by IR-OBIRCH

2015 ◽  
Author(s):  
Chunlei Wu ◽  
Berges Corinne
Keyword(s):  
Leakage Current ◽  
Fault Localization

TMR Magnetic Sensor Array Module for Detecting Leakage Current in Lithium-ion Batteries

2017 ◽  
Vol 137 (8) ◽  
pp. 481-486
Author(s):  
Junichi Hayasaka ◽  
Kiwamu Shirakawa ◽  
Nobukiyo Kobayashi ◽  
Kenichi Arai ◽  
Nobuaki Otake ◽  
...  
Keyword(s):  
Lithium Ion Batteries ◽  
Leakage Current ◽  
Sensor Array ◽  
Lithium Ion ◽  
Magnetic Sensor

Relationship between Leakage Current and Pollution Deposits on the Surface of Polymeric Insulator

2010 ◽  
Vol 130 (11) ◽  
pp. 1037-1041 ◽  
Author(s):  
Takuma Miyake ◽  
Yuya Seo ◽  
Tatsuya Sakoda ◽  
Masahisa Otsubo
Keyword(s):  
Leakage Current

Degradation and SILC Effects of RPECVD sub-2.0nm Oxide/Nitride and Oxynitride Dielectrics Under Constant Current Stress

2002 ◽  
Vol 716 ◽  
Author(s):  
Yi-Mu Lee ◽  
Yider Wu ◽  
Joon Goo Hong ◽  
Gerald Lucovsky
Keyword(s):  
Leakage Current ◽  
Electrical Performance ◽  
Constant Current ◽  
Continuous Increase ◽  
Current Stress ◽  
Thermal Oxide ◽  
Stress Induced Leakage Current ◽  
Boron Penetration ◽  
Soft Breakdown ◽  
Induced Defects

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.

Lightweight Fault Localization using Weighted Dynamic Control Flow Subgraph

2020 ◽  
Vol 16 (2) ◽  
pp. 214
Author(s):  
Wang Yong ◽  
Liu SanMing ◽  
Li Jun ◽  
Cheng Xiangyu ◽  
Zhou Wan
Keyword(s):  
Dynamic Control ◽  
Fault Localization ◽  
Control Flow

Circuit Voltage Probe Based on Time-Integrated Measurements of Optical Emission From Leakage Current

2002 ◽  
Author(s):  
Franco Stellari ◽  
Peilin Song ◽  
James C. Tsang ◽  
Moyra K. McManus ◽  
Mark B. Ketchen
Keyword(s):  
Leakage Current ◽  
Voltage Drop ◽  
Optical Emission ◽  
Channel Length ◽  
Operating Conditions ◽  
Power Circuit ◽  
Hot Carrier ◽  
Optical Inspection ◽  
Low Threshold ◽  
Circuit Power

Abstract Hot-carrier luminescence emission is used to diagnose the cause of excess quiescence current, IDDQ, in a low power circuit implemented in CMOS 7SF technology. We found by optical inspection of the chip that the high IDDQ is related to the low threshold, Vt, device process and in particular to transistors with minimum channel length (0.18 μm). In this paper we will also show that it is possible to gain knowledge regarding the operating conditions of the IC from the analysis of optical emission due to leakage current, aside from simply locating defects and failures. In particular, we will show how it is possible to calculate the voltage drop across the circuit power grid from time-integrated acquisitions of leakage luminescence.

A Manual Diagnosis Approach Using Targeted Fault Injection and Fault Simulation to Extend ATPG Diagnostic Resolution in Localizing Faults

2019 ◽  
Author(s):  
Rommel Estores ◽  
Karo Vander Gucht
Keyword(s):  
Fault Injection ◽  
Fault Simulation ◽  
Fault Localization ◽  
Pattern Generation ◽  
Test Coverage ◽  
Actual Case ◽  
Electrical Failure ◽  
Starting Point ◽  
Diagnostic Resolution ◽  
Diagnosis Approach

Abstract This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

2010 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Localization ◽  
Resistance Change ◽  
The Real ◽  
Analysis Techniques ◽  
Analysis Technique ◽  
Leakage Failure ◽  
Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

Fault Localization of Power-Ground Short via Signal Injection and Oscilloscope Technique

2010 ◽  
Author(s):  
Binh Nguyen
Keyword(s):  
Low Cost ◽  
Short Circuit ◽  
Fault Localization ◽  
Fault Isolation ◽  
Test Apparatus ◽  
Good Working ◽  
Signal Injection ◽  
Set Up ◽  
Non Destructive ◽  
Short Circuit Condition

Abstract For those attempting fault isolation on computer motherboard power-ground short issues, the optimal technique should utilize existing test equipment available in the debug facility, requiring no specialty equipment as well as needing a minimum of training to use effectively. The test apparatus should be both easy to set up and easy to use. This article describes the signal injection and oscilloscope technique which meets the above requirements. The signal injection and oscilloscope technique is based on the application of Ohm's law in a short-circuit condition. Two experiments were conducted to prove the effectiveness of these techniques. Both experiments simulate a short-circuit condition on the VCC3 power rail of a good working PC motherboard and then apply the signal injection and oscilloscope technique to localize the short. The technique described is a simple, low cost and non-destructive method that helps to find the location of the power-ground short quickly and effectively.

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