Topography and Deformation Measurement and FE Modeling applied to substrate-mounted large area wafer-level packages (including stacked dice and TSVs)

2010 ◽  
Author(s):  
M. Hert ◽  
S. Carniello ◽  
C. Cassidy
Keyword(s):  
Deformation Measurement ◽  
Fe Modeling ◽  
Wafer Level ◽  
Large Area

scholarly journals Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 342 ◽  
Author(s):  
Tanja Braun ◽  
Karl-Friedrich Becker ◽  
Ole Hoelck ◽  
Steve Voges ◽  
Ruben Kahle ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Form Factors ◽  
Heterogeneous Integration ◽  
Passive Component ◽  
Wafer Level ◽  
Large Area ◽  
Component Integration ◽  
Application Specific Integrated Circuit ◽  
Power Management Unit

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

Electrical Demonstration of TSV Interconnects and Multilevel Metallization for 3D Si Interposer Applications

2010 ◽  
Vol 2010 (1) ◽  
pp. 000007-000014 ◽  
Author(s):  
Erik Vick ◽  
Scott Goodwin ◽  
Dorota Temple
Keyword(s):  
Optimum Process ◽  
Process Conditions ◽  
Front Side ◽  
Wafer Level ◽  
Large Area ◽  
Test Vehicle ◽  
Dual Damascene ◽  
Damascene Process ◽  
Metal Levels ◽  
Metal Layers

A TSV test vehicle lot and 3D interposer demonstration lot were successfully fabricated and tested. Fabrication of the TSV test vehicle was accomplished using three process (mask) levels – front-side metal, backside TSV, and backside metal. The TSVs were formed using a vias-last approach with a nominal TSV size of 100μm, and an aspect ratio of 6:1. DRIE bottom clear process conditions were tested which produced 100 % yield on TSV contact chains with up to 540 vias. In addition, optimum process conditions resulted in a TSV resistance of 29 mΩ, and sufficient TSV isolation resistance (> 1MΩ) for the target application. The interposer demonstration lot incorporated five front-side metal levels, one TSV level, and two backside metal levels. The first four metal layers (M1-M4), utilized 2μm Cu and 2μm oxide layers. Metal layers M2-M4 were fabricated using a self-aligned dual damascene process. Each wafer in the demonstration lot had 4 MLM contact chain test structures, with 26400 vias per structure. On two wafers, 100 % yield was achieved on the MLM contact chains. For the dual damascene levels, average contact resistance per via was 4 mΩ. Functional testing was performed on two die from the demonstration lot (die size = 4 cm X 3.7 cm). Over 99 % of the functional nets (circuit paths) passed. Yield on large area test capacitors, tested at wafer level, exceeded 80 %.

scholarly journals Large-area integration of two-dimensional materials and their heterostructures by wafer bonding

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Arne Quellmalz ◽  
Xiaojing Wang ◽  
Simon Sawallich ◽  
Burkay Uzlu ◽  
Martin Otto ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Semiconductor Manufacturing ◽  
Large Scale ◽  
Hexagonal Boron Nitride ◽  
2D Materials ◽  
High Volume ◽  
Two Dimensional ◽  
Wafer Level ◽  
Large Area ◽  
Wide Range

AbstractIntegrating two-dimensional (2D) materials into semiconductor manufacturing lines is essential to exploit their material properties in a wide range of application areas. However, current approaches are not compatible with high-volume manufacturing on wafer level. Here, we report a generic methodology for large-area integration of 2D materials by adhesive wafer bonding. Our approach avoids manual handling and uses equipment, processes, and materials that are readily available in large-scale semiconductor manufacturing lines. We demonstrate the transfer of CVD graphene from copper foils (100-mm diameter) and molybdenum disulfide (MoS2) from SiO2/Si chips (centimeter-sized) to silicon wafers (100-mm diameter). Furthermore, we stack graphene with CVD hexagonal boron nitride and MoS2 layers to heterostructures, and fabricate encapsulated field-effect graphene devices, with high carrier mobilities of up to $$4520\;{\mathrm{cm}}^2{\mathrm{V}}^{ - 1}{\mathrm{s}}^{ - 1}$$ 4520 cm 2 V − 1 s − 1 . Thus, our approach is suited for backend of the line integration of 2D materials on top of integrated circuits, with potential to accelerate progress in electronics, photonics, and sensing.

Grid-based matching for full-field large-area deformation measurement

2015 ◽  
Vol 66 ◽  
pp. 307-319 ◽  
Author(s):  
Xian Du ◽  
Brian W. Anthony ◽  
Nigel C. Kojimoto
Keyword(s):  
Deformation Measurement ◽  
Large Area ◽  
Full Field ◽  
Grid Based

A Versatile Optical Head for 3D IC TSV Integration Process Control

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 002015-002049
Author(s):  
G. Fresquet
Keyword(s):  
Near Infrared ◽  
Optical Measurement ◽  
Wafer Level ◽  
Large Area ◽  
3D Integration ◽  
Infrared Wavelength ◽  
Quantitative Measurements ◽  
Defects Inspection ◽  
Die Bonding ◽  
Miniaturized Systems

3D Integration of miniaturized systems at wafer level generates new needs of metrology and defects inspection for the control of TSV geometries, temporary wafer bonding, wafer thinning, via interconnects technology and of wafer/die stacks. In this paper we demonstrate the capabilities of a versatile optical measurement system combining several microscopy and interferometry techniques in the visible and near infrared wavelength range. I. INTRODUCTION AND BACKGROUND ALL roadmaps predict a large spread of 3D heterogeneous integration technologies for the fabrication of miniaturized systems in the coming years1. Beside a large development of new fabrication processes, 3D integration generates new challenges in terms of metrology and defects inspection for wafer/die bonding, thinning and interconnection processes as well as for 3D architectures. Adaptation and/or combination of existing techniques and the development of new techniques become necessary in order to perform non destructive, fast and inspections or quantitative measurements on large area wafers with high lateral and vertical resolutions. In this work we describe results obtained with an optical system combining several microscopy and interferometry techniques.

Wafer-level composite mold for large-area nanoimprint lithography

2018 ◽  
Vol 26 (4) ◽  
pp. 894-905
Author(s):  
兰红波 LAN Hong-bo ◽  
郭良乐 GUO Liang-le ◽  
许权 XU Quan ◽  
钱垒 QIAN Lei
Keyword(s):  
Nanoimprint Lithography ◽  
Wafer Level ◽  
Large Area

Packaging and Assembly Challenges for 2.5D/3D Devices

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001161-001191 ◽  
Author(s):  
Gerald Beyer ◽  
Kenneth Rebibis ◽  
Arnita Podpod ◽  
Francisco Cadacio ◽  
Teng Wang ◽  
...  
Keyword(s):  
Flip Chip ◽  
Mechanical Stability ◽  
Coefficient Of Thermal Expansion ◽  
Wafer Level ◽  
Large Area ◽  
Molding Process ◽  
Process Step ◽  
Joint Formation ◽  
Bonding Force ◽  
Underfill Material

The continuous development of 2.5D/3D packaging and stack assembly technologies has enabled different ways of producing advanced packages for the said devices. Advancement in D2D, D2W and W2W bonding have allowed these devices to be a step closer to being fully manufactured in volume. Thermo-compression bonding (TCB) process in combination with a pre-applied underfill material (WLUF/NUF) have been developed and investigated for assembling 2.5D and 3D devices with fine pitch (10μm - 40 μm) μbumps. This assembly step though developed, is not without challenges. There is a need to select the right underfill material based on its mechanical and chemical properties which could contribute to issues such as die warping, voiding and non-wetting of μbumps. These materials should also be able to withstand several thermal steps within the entire stack assembly process and is able to pass reliability testing. During the TCB process, bonding forces have a profound impact on the joint formation behavior on the μbumps. A low bonding force could produce a joint formation with a lot of underfill filler entrapment and an incomplete reaction of the solder. A higher bonding force leads to more solder squeezing-out, leaving a thin and completely reacted intermetallic compound (IMC) layer in the joints. The D2D, D2W and W2W assembled chips can then be packaged into a standard flip chip component using laminate BGA substrates. But even with this volume manufacturing process, the introduction of 2.5D/3D stack devices brings another set of challenges to an existing assembly infrastructure. Challenges such as the handling of the stacked devices, the CTE mismatches of an entirely new set of materials and the constant scaling in FC bump (Cu Pillar or C4) pitches in an existing infrastructure remain. The limitations of organic BGA packages in terms of CTE mismatches and costs gave rise to Fan-out Wafer Level Packages (FOWLP) or a technique also known as wafer reconstruction. However, there are certain tradeoffs particularly in the molding process step of fully D2W stacked or reconstructed 300 mm wafers. Molding such a large area of stacked chips with very narrow gaps of around 50μm to 300μm is a major challenge especially in trying to maintain the flatness of the wafer for succeeding wafer level processing steps. The large warpage of over molded (D2W or reconstructed) wafers is due to the coefficient of thermal expansion (CTE) mismatch between silicon and the reconstruction material. Therefore careful selection of materials and design of reconstructed structures is needed. Other techniques to keep the D2W or reconstructed assemblies are being developed and evaluated. Also by selecting an FOWLP or reconstructed wafer type of package, the integration of temporary bonding materials (TBMs) in TCB and wafer molding becomes a challenge. In order to produce the reconstructed wafer or the thinned D2W assembly, thermal and mechanical stability is required for such a material. In summary, the combination of advance stacking techniques and materials within certain 2.5D/3D integration flows could produce a low-cost and reliable 3D package. But these combinations will pose a number of challenges that needs to be addressed. This paper will discuss the different integration flows, stacking and packaging assembly techniques (and their challenges) that could make volume manufacturing possible for 2.5D/3D devices in the future.

scholarly journals Synthesis of few-layer 2H-MoSe2 thin films with wafer-level homogeneity for high-performance photodetector

Nanophotonics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 1959-1969 ◽  
Author(s):  
Tian-Jun Dai ◽  
Yu-Chen Liu ◽  
Xu-Dong Fan ◽  
Xing-Zhao Liu ◽  
Dan Xie ◽  
...  
Keyword(s):  
Thin Films ◽  
High Performance ◽  
Deep Understanding ◽  
Chemical Vapor ◽  
Atomic Layer ◽  
Fast Response ◽  
Wafer Level ◽  
Large Area ◽  
Carrier Recombination ◽  
Layer Deposition

AbstractThe unique structural and physical properties of two-dimensional (2D) atomic layer semiconductors render them promising candidates for electronic or optoelectronic devices. However, the lack of efficient and stable approaches to synthesize large-area thin films with excellent uniformity hinders their realistic applications. In this work, we reported a method involving atomic layer deposition and a chemical vapor deposition chamber to produce few-layer 2H-MoSe2 thin films with wafer-level uniformity. The reduction of MoO3 was found indispensable for the successful synthesis of MoSe2 films due to the low vaporization temperature. Moreover, a metal-semiconductor-metal photodetector (PD) was fabricated and investigated systematically. We extracted an ultrahigh photoresponsivity approaching 101 A/W with concomitantly high external quantum efficiency up to 19,668% due to the produced gain arising from the holes trapped at the metal/MoSe2 interface, the band tail state contribution, and the photogating effect. A fast response time of 22 ms was observed and attributed to effective nonequilibrium carrier recombination. Additionally, the ultrahigh photoresponsivity and low dark current that originated from Schottky barrier resulted in a record-high specific detectivity of up to 2×1013 Jones for 2D MoSe2/MoS2 PDs. Our findings revealed a pathway for the development of high-performance PDs based on 2D MoSe2 that are inexpensive, large area, and suitable for mass production and contribute to a deep understanding of the photoconductivity mechanisms in atomically thin MoSe2. We anticipate that these results are generalizable to other layer semiconductors as well.

Convergent Beam Electron Diffraction

1978 ◽  
Vol 36 (3) ◽  
pp. 304-315
Author(s):  
G. Lehmpfuhl
Keyword(s):  
Electron Diffraction ◽  
Diffraction Pattern ◽  
Crystal Surface ◽  
Diffraction Spot ◽  
Crystal Thickness ◽  
Large Area ◽  
Electron Microscopic ◽  
Additional Information ◽  
Microscopic Investigations

Introduction In electron microscopic investigations of crystalline specimens the direct observation of the electron diffraction pattern gives additional information about the specimen. The quality of this information depends on the quality of the crystals or the crystal area contributing to the diffraction pattern. By selected area diffraction in a conventional electron microscope, specimen areas as small as 1 µ in diameter can be investigated. It is well known that crystal areas of that size which must be thin enough (in the order of 1000 Å) for electron microscopic investigations are normally somewhat distorted by bending, or they are not homogeneous. Furthermore, the crystal surface is not well defined over such a large area. These are facts which cause reduction of information in the diffraction pattern. The intensity of a diffraction spot, for example, depends on the crystal thickness. If the thickness is not uniform over the investigated area, one observes an averaged intensity, so that the intensity distribution in the diffraction pattern cannot be used for an analysis unless additional information is available.

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