FEM analysis of SnAgCu solder joint in flip chip

2009 ◽  
Author(s):  
Yongchang ◽  
Yan Xiaoyan Li ◽  
Na Liu
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Fem Analysis ◽  
Snagcu Solder

Experimental evaluation of SnAgCu solder joint reliability in 100-μm pitch flip-chip assemblies

2014 ◽  
Vol 54 (5) ◽  
pp. 939-944 ◽  
Author(s):  
Ye Tian ◽  
Xi Liu ◽  
Justin Chow ◽  
Yi Ping Wu ◽  
Suresh K. Sitaraman
Keyword(s):  
Solder Joint ◽  
Experimental Evaluation ◽  
Flip Chip ◽  
Solder Joint Reliability ◽  
Snagcu Solder ◽  
Joint Reliability

Overview of Fatigue Failure of Pb-Free Solder Joints in CSP/BGA/Flip-Chip Applications

2009 ◽  
Vol 6 (3) ◽  
pp. 149-153 ◽  
Author(s):  
Sean M. Chinen ◽  
Matthew T. Siniawski
Keyword(s):  
Finite Element ◽  
Solder Joint ◽  
Finite Element Methods ◽  
Flip Chip ◽  
Snagcu Solder ◽  
Design Considerations ◽  
Mode Of Failure ◽  
Solder Joint Fatigue ◽  
Free Solder

The purpose of this paper is to provide an overview of SnAgCu solder joint fatigue in BGA/CSP/flip-chip applications and the concern of long-term reliability. The most common mode of failure is ductile fracture due to creep strain. Several methods of predicting the overall life of the solder joint are the Coffin-Manson approach, a constitutive fatigue law, and a damage based model using FEM (finite element methods). The effects of underfill and its processes as well as design considerations that will increase reliability will also be discussed.

Evaluation of solder joint reliability in flip chip package under thermal shock test

2006 ◽  
Vol 504 (1-2) ◽  
pp. 426-430 ◽  
Author(s):  
Dae-Gon Kim ◽  
Jong-Woong Kim ◽  
Seung-Boo Jung
Keyword(s):  
Solder Joint ◽  
Thermal Shock ◽  
Flip Chip ◽  
Thermal Shock Test ◽  
Solder Joint Reliability ◽  
Shock Test ◽  
Joint Reliability

Vibration Analysis Based Modeling and Defect Recognition for Flip Chip Solder Joint Inspection

2000 ◽  
Author(s):  
Sheng Liu ◽  
Dathan Erdahl ◽  
I. Charles Ume
Keyword(s):  
Solder Joint ◽  
Vibration Analysis ◽  
Flip Chip ◽  
Process Development ◽  
Great Promise ◽  
Quality Inspection ◽  
Vibration Frequencies ◽  
Vibration Responses ◽  
Solder Joint Inspection ◽  
Joint Quality

Abstract A novel approach for flip chip solder joint quality inspection based on vibration analysis is presented. Traditional solder joint inspection methods have their limitations when applied to flip chip solder joint quality inspection. The vibration detection method is a new approach which has advantages such as being non-contact, non-destructive, fast and can be used on-line or during process development. In this technique, a flip chip was modeled as a thick plate supported by solder bumps. Changes in solder joint quality produce different vibration responses of flip chip, and change its natural vibration frequencies. In this paper, the vibration frequencies of a flip chip on a ceramic substrate were calculated using the finite element method. Based on vibration analysis, a laser ultrasound and interferometric system was developed for flip chip solder joint quality inspection. In this system, chips with good solder joints can be distinguished from chips with bad joints using their vibration responses and frequencies. Defects recognition methods were developed and tested. Results indicate this approach offers great promise for solder bump inspection in flip chip, BGA and chip scale packages.

Development of Lead-Free Flip Chip Package and Its Reliability

2003 ◽  
Author(s):  
Jeffrey C. B. Lee ◽  
Sting Wu ◽  
H. L. Chou ◽  
Yi-Shao Lai
Keyword(s):  
Failure Mode ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Wire Bonding ◽  
Point Of View ◽  
Lead Free ◽  
Temperature Cycle ◽  
Snagcu Solder ◽  
Temperature Cycle Test

SnAgCu solder used in laminate package like PBGA and CSP BGA to replace eutectic SnPb as interconnection has become major trend in the electronic industry. But unlike well-known failure mode of wire bonding package, flip chip package with SnAgCu inner solder bump and external solder ball as electrical interconnection present a extremely different failure mode with wire-bonding package from a point of view in material and process. In this study, one 16mm×16mm 3000 I/O SnAgCu wafer bumping using screen-printing process was explored including the effects of reflow times, high temperature storage life (HTSL) and temperature cycle test (TCT) on bump shear strength. Furthermore, the qualified wafer bumping is assembled by flip chip assembly with various underfill material and specific organic build-up substrate, then is subject to MSL4/260°C precondition and temperature cycle test to observe the underfill effect on SnAgCu bump protection and solder joint life. Various failure modes in the flip chip package like solder bump, underfill and UBM and so on, will be scrutinized with SEM. And finally, best material combination will be addressed to make the lead free flip package successful.

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