Reliability of Cu pillar bump for flip chip and 3-D SiP

2008 ◽  
Author(s):  
Byoung-Joon Kim ◽  
Gi-Tae Lim ◽  
Jaedong Kim ◽  
Kiwook Lee ◽  
Young-Bae Park ◽  
...  
Keyword(s):  
Flip Chip ◽  
Cu Pillar ◽  
Cu Pillar Bump

Cu Pillar Bump Design Parameters for Flip Chip Integration

2021 ◽  
Author(s):  
Shengmin Wen ◽  
Jason Goodelle ◽  
VanDee Moua ◽  
Kenny Huang ◽  
Chris Xiao
Keyword(s):  
Flip Chip ◽  
Design Parameters ◽  
Cu Pillar ◽  
Cu Pillar Bump

Effect of preformed IMC Layer on Electromigration of Solder Capped Cu Pillar Bump Interconnection on an organic substrate

2012 ◽  
Vol 2012 (1) ◽  
pp. 000455-000463 ◽  
Author(s):  
Yasumitsu Orii ◽  
Kazushige Toriyama ◽  
Sayuri Kohara ◽  
Hirokazu Noma ◽  
Keishi Okamoto ◽  
...  
Keyword(s):  
Flip Chip ◽  
Organic Substrate ◽  
Stress Tests ◽  
Cross Sectional ◽  
Current Stress ◽  
Barrier Layers ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Cu Pillar Bump ◽  
Cu Dissolution

The electromigration behavior of 80 μm pitch solder capped Cu pillar bump interconnection on an organic carrier is studied and discussed. Recently the solder capped Cu pillar bump technology has been widely used in mobile applications as a peripheral ultra fine pitch flip chip interconnection technique. The solder capped Cu pillar bumps are formed on Al pads which are commonly used in wirebonding technique. It allows us an easy control of the space between the die and the substrate simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. Solder capped Cu pillar bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with a no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. It is an ideal technology for the systems requiring fine pitch structures. In 2011, the EM tests were performed on 80 μm pitch solder capped Cu pillar bump interconnections and the effects of Ni barrier layers on the Cu pillars and the preformed intermetallic compound (IMC) layers on the EM tests were studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height was 45 μm and the solder height was 25 μm. The solder composition was Sn-2.5Ag. Aged condition for pre-formed IMCs was 2,000 hours at 150°C. It was shown that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in reducing the Cu atoms dissolution. In this report, it is studied that which of the IMC layers, Cu3Sn or Cu6Sn5, is more effective in preventing the Cu atom dissolution. The cross-sectional analyses of the joints after the 2000 hours of the test with 7kA/cm2 at 170°C were performed for this purpose. The relationship between the thickness of Cu3Sn IMC layer and the Cu migration is also studied by performing the current stress tests on the joints with controlled Cu3Sn IMC thicknesses. The samples were thermally aged prior to the tests at a higher temperature (200°C) and in a shorter time (10–50 hours) than the previous experiments. The cross-sectional analyses of the Sn-2.5Ag joints without pre-aging consisting mostly of Cu6Sn5, showed a significant Cu dissolution while the Cu dissolution was not detected for the pre-aged joints with thick Cu3Sn layers. A large number of Kirkendall voids were also observed in the joints without pre-aging. The current stress tests on the controlled Cu3Sn joints showed that Cu3Sn layer thickness of more than 1.5 μm is effective in reducing Cu dissolution in the joints.

Cu Pillar Bumping Technology with Solder Alloy Versatility

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002360-002376
Author(s):  
Guy Burgess ◽  
Anthony Curtis ◽  
Tom Nilsson ◽  
Gene Stout ◽  
Theodore G. Tessier
Keyword(s):  
Solder Alloy ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Solder Paste ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Cu Pillar Bump ◽  
Wide Range ◽  
Method Of Production ◽  
Board Level

There is considerable interest in the semiconductor industry regarding Cu pillar bumping for finer pitch flip chip and 3D packaging applications. A common Cu Pillar method of production incorporates a combined Cu plated post topped with a plated solder pillar cap, usually of a Sn or SnAg alloy. Compared with this, a unique method of Cu pillar bump production developed at FlipChip International, LLC (FCI) creates the solder cap by applying and reflowing a solder paste on top of the plated Cu post. This method of production offers several benefits; the most important include a broader solder alloy selection, better alloy control, and improved overall pillar height uniformity. FCI has qualified a wide range of Cu pillar bump sizes, heights and shapes including Cu pillar bumps for fine pitch applications as low as 35um pitch (NANOPillarTM). FCI's Cu pillar bump structures in overmolded SiP have passed JEDEC 22-A104C board level thermal cycle testing, JEDEC J-STD-20A MLS 3@260C, as well as other board level corrosion and shock testing. FCI has demonstrated capping Cu pillar bumps with a broad range of solder alloys tailored to specific application requirements.

Cu pillar bump flip chip package development for advanced node chip

2015 ◽  
Author(s):  
Chung Yen Wu ◽  
Cheng Hsiao Wang ◽  
Kai Kuang Ho ◽  
Kuo Ming Chen ◽  
Po Chen Kuo ◽  
...  
Keyword(s):  
Flip Chip ◽  
Cu Pillar ◽  
Cu Pillar Bump

An RDL UBM Structural Design for Solving Ultralow-K Delamination Problem of Cu Pillar Bump Flip Chip BGA Packaging

2014 ◽  
Vol 43 (11) ◽  
pp. 4229-4240 ◽  
Author(s):  
K. M. Chen ◽  
C. Y. Wu ◽  
C. H. Wang ◽  
H. C. Cheng ◽  
N. C. Huang
Keyword(s):  
Structural Design ◽  
Flip Chip ◽  
Cu Pillar ◽  
Cu Pillar Bump

Cu Pillar Bump FCBGA Package Design and Reliability Assessments

2008 ◽  
Author(s):  
Nicholas Kao ◽  
Yen-Chang Hu ◽  
Yuan-Lin Tseng ◽  
Eason Chen ◽  
Jeng-Yuan Lai ◽  
...  
Keyword(s):  
Stress Distribution ◽  
High Performance ◽  
Flip Chip ◽  
Spherical Geometry ◽  
Electrical Performance ◽  
Design Factor ◽  
Cu Pillar ◽  
Chip Technology ◽  
Cu Pillar Bump ◽  
Low K

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more Input/Output (I/O) and better electrical characteristics under same package form factor. Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pin accommodation and high transmission speed. However, the flip chip technology is encountering its structure limitation as the bump pitch is getting smaller and smaller because the spherical geometry bump shape is to limit the fine bump pitch arrangement and it’s also difficult to fill by underfill between narrow gaps. As this demand, a new fine bump pitch technology is developed as “Cu pillar bump” with the structure of Cu post and solder tip. The Cu pillar bump is plating process manufactured structure and composes with copper cylinder (Cu post) and mushroom shape solder cap (Solder tip). The geometry of Cu pillar bump not only provides a finer bump pitch, but also enhances the thermal performances due to the higher conductivity than conventional solder material. This paper mainly characterized the Cu pillar bump structure stress performances of FCBGA package to prevent reliability failures by finite element models. First, the bump stress and Cu/low-k stress of Cu pillar bump were studied to compare with conventional bump structure. The purpose is to investigate the potential reliability risk of Cu pillar bump structure. Secondly, the bump stress and Cu/low-k stress distribution were evaluated for different Polyimide (PI) layer, Under Bump Metallization (UBM) size and solder mask opening (SMO) size. This study can show the stress contribution of each design factor. Thirdly, a matrix which combination UBM size, Cu post thickness, SMO size, PI opening and PI thickness were studied to observe the stress distribution. Finally, the stress simulation results were experimentally validated by reliability tests.

scholarly journals Interfacial reaction and failure mechanism of Cu/Ni/SnAg1.8/Cu flip chip Cu pillar bump under thermoelectric stresses

2018 ◽  
Vol 67 (2) ◽  
pp. 028101
Author(s):  
Zhou Bin ◽  
Huang Yun ◽  
En Yun-Fei ◽  
Fu Zhi-Wei ◽  
Chen Si ◽  
...  
Keyword(s):  
Failure Mechanism ◽  
Interfacial Reaction ◽  
Flip Chip ◽  
Cu Pillar ◽  
Cu Pillar Bump

Effects of Silicon Wafer Bump Pad Structures on Solder and Cu Pillar Flip-Chip Reliability

2016 ◽  
Vol 2016 (1) ◽  
pp. 000100-000105
Author(s):  
Shirley Asoy ◽  
Scott Exon ◽  
Liping Zhu ◽  
Peter Moon ◽  
Michael Carroll ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Flip Chip ◽  
Failure Modes ◽  
Metal Layer ◽  
Production Environment ◽  
Large Area ◽  
Cu Pillar ◽  
Lack Of Information ◽  
Cu Pillar Bump ◽  
Volume Production

Abstract Solder and Cu pillar flip-chip silicon die technologies have been widely used in chip to package mobile module products. During the early design phase, integrated circuit (IC) designers usually apply standard bump design rules, due to lack of information on the reliability of the metal layer stack-up with different bumping processes. However, module reliability data has demonstrated that the stack-up and thickness of the metal layers in a silicon die has a great effect on package stresses, especially for large area Cu pillar flip chip die. In this paper, the effects of bump pad structures on solder and Cu pillar bump reliability have been investigated. A 3D mechanical stress model was developed to compare and optimize various bump structures. A test vehicle with die and module was designed and assembled in a volume production environment. Assembly in-line data was collected and analyzed, and is presented in this paper. Reliability testing and failure analysis were performed to verify the failure modes. Guidelines for designing solder and Cu Pillar Flip-chip bump pad structures have been developed, and are presented in this paper.

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