Electrical characterization of SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/ stacked gate oxides on strained-Si

2004 ◽  
Author(s):  
C.K. Maiti ◽  
S.K. Samanta ◽  
G.K. Dalapati ◽  
S. Chatterjee
Keyword(s):  
Electrical Characterization ◽  
Strained Si ◽  
Gate Oxides

Electrical characterization of TiO2 gate oxides on strained-Si

2004 ◽  
Vol 72 (1-4) ◽  
pp. 253-256 ◽  
Author(s):  
C.K. Maiti ◽  
S.K. Samanta ◽  
G.K. Dalapati ◽  
S.K. Nandi ◽  
S. Chatterjee
Keyword(s):  
Electrical Characterization ◽  
Strained Si ◽  
Gate Oxides

Evaluation Of 2.0 nm Grown and Deposited Dielectrics in 0.1 μm PMOSFETs

1998 ◽  
Vol 525 ◽  
Author(s):  
A. Srivastava ◽  
H. H. Heinisch ◽  
E. Vogel ◽  
C. Parker ◽  
C. M. Osburn ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Deposition Process ◽  
Gate Oxides ◽  
Boron Doped ◽  
Excellent Control ◽  
Lower Temperature ◽  
Boron Penetration

ABSTRACTThe quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.

Electrical characterization of ultra-thin gate oxides on Si/Si1-x-yGexCy/Si quantum well heterostructures

2000 ◽  
Vol 15 (7) ◽  
pp. 761-765 ◽  
Author(s):  
S Maikap ◽  
S K Ray ◽  
S John ◽  
S K Banerjee ◽  
C K Maiti
Keyword(s):  
Quantum Well ◽  
Electrical Characterization ◽  
Gate Oxides

Implementation of Sub-Resolvable Features for Precise Electrical Characterization of SiC Gate Oxide Parameters

2012 ◽  
Vol 717-720 ◽  
pp. 797-800
Author(s):  
J. Jay McMahon ◽  
Liang Chun Yu ◽  
Jody Fronheiser ◽  
J.T. Elson ◽  
Roger Kovalec ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Screening Tests ◽  
Compensation Mechanism ◽  
Gate Oxides ◽  
Attractive Option ◽  
Van Der Pauw ◽  
Similar Yield

We describe fabrication of Van der Pauw (VDP) structures for characterization of gate oxides grown on 4H SiC epi surfaces. Implementation of sub-resolvable features (SRF) as a corner compensation mechanism is analyzed with challenges and advantages presented. Results of on-wafer screening tests suggest that implementation of SRFs widens tolerance for misalignment, producing similar yield between uncompensated VDPs with 0.2 micron overlap and compensated VDPs with 0.1 micron overlap for structures with best alignment. Optimization of SRFs for SiC could be an attractive option for extending lithographic capability in advanced devices.

Electrical characterization of low thermal budget gate oxides on Si/Si0.8Ge0.2/Si substrates

2002 ◽  
Vol 46 (7) ◽  
pp. 991-995 ◽  
Author(s):  
Alok Sareen ◽  
Ann-Chatrin Lindgren ◽  
Per Lundgren ◽  
Stefan Bengtsson
Keyword(s):  
Electrical Characterization ◽  
Gate Oxides ◽  
Thermal Budget ◽  
Si Substrates ◽  
Low Thermal Budget

Electrical characterization of transfer transistors with pure and nitirided gate oxides in four-transistor CMOS image pixels

2008 ◽  
Vol 23 (7) ◽  
pp. 075032
Author(s):  
Young-Joo Song ◽  
Vetpany Sivongsay ◽  
Khampone Mounphoumy ◽  
Bounmy Phanthavong ◽  
Vathsana Khanmvongsa ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxides ◽  
Image Pixels

Using AFM Related Techniques for the Nanoscale Electrical Characterization of Irradiated Ultrathin Gate Oxides

2007 ◽  
Vol 54 (6) ◽  
pp. 1891-1897 ◽  
Author(s):  
M. Porti ◽  
S. Gerardin ◽  
M. NafrÍa ◽  
X. Aymerich ◽  
A. Cester ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxides
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