Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process

2002 ◽  
Author(s):  
Ming-Dou Ker ◽  
Kei-Kang Hung ◽  
H.T.-H. Tang ◽  
S.-C. Huang ◽  
S.-S. Chen ◽  
...  
Keyword(s):  
Cmos Process ◽  
Esd Protection ◽  
Protection Circuits

ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process

2007 ◽  
Author(s):  
Yuan-Wen Hsiao ◽  
Ming-Dou Ker ◽  
Po-Yen Chiu ◽  
Chun Huang ◽  
Yuh-Kuang Tseng
Keyword(s):  
High Speed ◽  
Cmos Process ◽  
Esd Protection

Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On

ETRI Journal ◽  
2009 ◽  
Vol 31 (6) ◽  
pp. 725-731 ◽  
Author(s):  
Yong-Seo Koo ◽  
Kwangsoo Kim ◽  
Shihong Park ◽  
Kwidong Kim ◽  
Jong-Kee Kwon
Keyword(s):  
Leakage Current ◽  
Turn On ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Esd Protection ◽  
Protection Circuits

ESD protection design for wideband RF applications in 65-nm CMOS process

2014 ◽  
Author(s):  
Li-Wei Chu ◽  
Chun-Yu Lin ◽  
Ming-Dou Ker ◽  
Ming-Hsiang Song ◽  
Jen-Chou Tseng ◽  
...  
Keyword(s):  
Cmos Process ◽  
Esd Protection ◽  
Rf Applications
Sign in / Sign up

Export Citation Format

Share Document