A latch-up immunized lateral trench-gate conductivity modulated power transistor

1999 ◽  
Author(s):  
Jun Cai ◽  
Keng Foo Lo ◽  
J.K.O. Sin
Keyword(s):  
Power Transistor ◽  
Latch Up

Latch-Up Induced Slit Voiding in Aluminum Metal Lines

1999 ◽  
Author(s):  
Chunyu Zhang ◽  
Lakshmi Vedula ◽  
Shekhar Khandekar
Keyword(s):  
High Temperature ◽  
Line Width ◽  
Fold Increase ◽  
Metal Line ◽  
Operating Life ◽  
Mixed Signal ◽  
Aluminum Metal ◽  
Temperature Operating ◽  
Latch Up

Abstract Latch-up induced during High Temperature Operating Life (HTOL) test of a mixed signal device fabricated with 1.0 μm CMOS, double poly, double metal process caused failures due to an open in aluminum metal line. Metal lines revealed wedge voids of about 50% of the line width. Triggering of latch up mechanism during the HTOL test resulted in a several fold increase of current flowing through the ground metal line. This increase in current resulted in the growth of the wedge voids leading to failures due to open metal lines.

A Silicon Debugging Methodology on Customer Prototype for Wafer Foundries

2012 ◽  
Author(s):  
Mai Zhihong ◽  
Ng Tsu Hau ◽  
Dawood M. Khalid ◽  
Tan Pik Kee ◽  
Jeffrey Lam
Keyword(s):  
Case Studies ◽  
Semiconductor Industry ◽  
Full Information ◽  
Limited Information ◽  
Ip Protection ◽  
First Case ◽  
Silicon Debugging ◽  
Failure Location ◽  
Device Chip ◽  
Latch Up

Abstract IP protection is of major importance for a semiconductor company and only limited information is made available for device debugging for the product outsourced to a foundry. In order to position ourselves better in the ever competitive semiconductor industry, with the consideration of IP protection, we have to provide the customers with the Si debugging capability and device/chip verification services in foundry. This paper explores the Si debugging methodology and technique in a foundry. Two case studies are presented and discussed. The first case illustrates the isolation of the failure location by InGaAs microscopy, upon which the failure was identified to be caused by a latch-up issue. In the second case, due to confidentiality considerations from the customer, full information could not be provided to the foundry for silicon debugging. The paper illustrates the ability to effectively debug a failure despite being constrained by limited information from the customer.

РАДИАЦИОННО СТОЙКОЕ КМОП СТАТИЧЕСКОЕ ОЗУ 16 МБИТ 1657РУ2У

2020 ◽  
Vol 96 (3s) ◽  
pp. 169-174
Author(s):  
Ю.М. Герасимов ◽  
Н.Г. Григорьев ◽  
А.В. Кобыляцкий ◽  
Я.Я. Петричкович
Keyword(s):  
Total Dose ◽  
Heavy Particles ◽  
Topological Features ◽  
Radiation Hardened ◽  
Latch Up

Рассматриваются архитектурные, схемотехнические и конструктивно-топологические особенности асинхронного радиационно стойкого ОЗУ 1657РУ2У емкостью 16 Мбит с организацией (1Мx16)/(2Mx8), изготавливаемого по коммерческой КМОП-технологии объемного кремния уровня 130 нм. СБИС ОЗУ нечувствительна к эффекту «защелкивания», имеет повышенные дозовую стойкость и сбоеустойчивость при воздействии отдельных ядерных частиц (ОЯЧ), протонов и нейтронов (ТЧ). The paper highlights architectural, schematic and topological features of the radiation hardened 16 Mbit CMOS SRAM with configurable organization 1Mx16/2Mx8, which is immune to latch-up and with improved total dose and heavy particles tolerance.

2.5 W, C-band, GaAs/AlGaAs heterojunction bipolar power transistor

1989 ◽  
Vol 25 (15) ◽  
pp. 979 ◽  
Author(s):  
A.P. Long ◽  
I.H. Goodridge ◽  
J.P. King ◽  
A.J. Holden ◽  
J.G. Metcalfe ◽  
...  
Keyword(s):  
Power Transistor

A 4 GHz High Power Transistor - Design and Reliability

1973 ◽  
Author(s):  
P. Wang ◽  
J. Chen ◽  
P. Froess ◽  
S. Kakihana
Keyword(s):  
High Power ◽  
Power Transistor
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