Modeling Cooperative Threads to Project GPU Performance for Adaptive Parallelism

2015 ◽  
Author(s):  
Jiayuan Meng ◽  
Thomas D. Uram ◽  
Vitali Morozov ◽  
Venkatram Vishwanath ◽  
Kalyan Kumaran
Keyword(s):  
Adaptive Parallelism

scholarly journals Transparent adaptive parallelism on NOWs using OpenMP

1999 ◽  
Vol 34 (8) ◽  
pp. 96-106 ◽  
Author(s):  
Alex Scherer ◽  
Honghui Lu ◽  
Thomas Gross ◽  
Willy Zwaenepoel
Keyword(s):  
Adaptive Parallelism

scholarly journals Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 230
Author(s):  
Jaechan Cho ◽  
Yongchul Jung ◽  
Seongjoo Lee ◽  
Yunho Jung
Keyword(s):  
Neural Networks ◽  
High Throughput ◽  
Deep Neural Networks ◽  
State Of The Art ◽  
Throughput Performance ◽  
Adaptive Parallelism ◽  
Sensor Applications ◽  
Binary Neural Network ◽  
Target Layer ◽  
Network Topologies

Binary neural networks (BNNs) have attracted significant interest for the implementation of deep neural networks (DNNs) on resource-constrained edge devices, and various BNN accelerator architectures have been proposed to achieve higher efficiency. BNN accelerators can be divided into two categories: streaming and layer accelerators. Although streaming accelerators designed for a specific BNN network topology provide high throughput, they are infeasible for various sensor applications in edge AI because of their complexity and inflexibility. In contrast, layer accelerators with reasonable resources can support various network topologies, but they operate with the same parallelism for all the layers of the BNN, which degrades throughput performance at certain layers. To overcome this problem, we propose a BNN accelerator with adaptive parallelism that offers high throughput performance in all layers. The proposed accelerator analyzes target layer parameters and operates with optimal parallelism using reasonable resources. In addition, this architecture is able to fully compute all types of BNN layers thanks to its reconfigurability, and it can achieve a higher area–speed efficiency than existing accelerators. In performance evaluation using state-of-the-art BNN topologies, the designed BNN accelerator achieved an area–speed efficiency 9.69 times higher than previous FPGA implementations and 24% higher than existing VLSI implementations for BNNs.

Adaptive parallelism and Piranha

Computer ◽  
1995 ◽  
Vol 28 (1) ◽  
pp. 40-49 ◽  
Author(s):  
N. Carriero ◽  
E. Freeman ◽  
D. Gelernter ◽  
D. Kaminsky
Keyword(s):  
Adaptive Parallelism
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