VARSHA: Variation and Reliability-Aware Application Scheduling with Adaptive Parallelism in the Dark-Silicon Era

2015 ◽  
Author(s):  
Nishit Kapadia ◽  
Sudeep Pasricha
Keyword(s):  
Dark Silicon ◽  
Adaptive Parallelism

scholarly journals Transparent adaptive parallelism on NOWs using OpenMP

1999 ◽  
Vol 34 (8) ◽  
pp. 96-106 ◽  
Author(s):  
Alex Scherer ◽  
Honghui Lu ◽  
Thomas Gross ◽  
Willy Zwaenepoel
Keyword(s):  
Adaptive Parallelism

scholarly journals Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 230
Author(s):  
Jaechan Cho ◽  
Yongchul Jung ◽  
Seongjoo Lee ◽  
Yunho Jung
Keyword(s):  
Neural Networks ◽  
High Throughput ◽  
Deep Neural Networks ◽  
State Of The Art ◽  
Throughput Performance ◽  
Adaptive Parallelism ◽  
Sensor Applications ◽  
Binary Neural Network ◽  
Target Layer ◽  
Network Topologies

Binary neural networks (BNNs) have attracted significant interest for the implementation of deep neural networks (DNNs) on resource-constrained edge devices, and various BNN accelerator architectures have been proposed to achieve higher efficiency. BNN accelerators can be divided into two categories: streaming and layer accelerators. Although streaming accelerators designed for a specific BNN network topology provide high throughput, they are infeasible for various sensor applications in edge AI because of their complexity and inflexibility. In contrast, layer accelerators with reasonable resources can support various network topologies, but they operate with the same parallelism for all the layers of the BNN, which degrades throughput performance at certain layers. To overcome this problem, we propose a BNN accelerator with adaptive parallelism that offers high throughput performance in all layers. The proposed accelerator analyzes target layer parameters and operates with optimal parallelism using reasonable resources. In addition, this architecture is able to fully compute all types of BNN layers thanks to its reconfigurability, and it can achieve a higher area–speed efficiency than existing accelerators. In performance evaluation using state-of-the-art BNN topologies, the designed BNN accelerator achieved an area–speed efficiency 9.69 times higher than previous FPGA implementations and 24% higher than existing VLSI implementations for BNNs.

FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era

2017 ◽  
Vol 28 (7) ◽  
pp. 1905-1918 ◽  
Author(s):  
Lei Yang ◽  
Weichen Liu ◽  
Weiwen Jiang ◽  
Mengquan Li ◽  
Peng Chen ◽  
...  
Keyword(s):  
Network On Chip ◽  
Dark Silicon ◽  
Systems On Chip ◽  
On Chip ◽  
Many Core

Exploração do espaço de projeto em arquiteturas heterogêneas cientes de dark silicon e utilizando computação aproximada

2020 ◽  
Author(s):  
Daniela Catalan ◽  
Ricardo Ribeiro Dos Santos
Keyword(s):  
Dark Silicon

O problema de dark silicon surgiu com o incremento da corrente de fuga em consequência da miniaturização dos transistores. Pesquisas a fim de encontrar soluções para mitigar o dark silicon têm sido estudadas, muitas delas propondo a heterogeneidade de dispositivos de processamento. Contudo, o aumento da diversidade de dispositivos e dos objetivos na definição de sistemas heterogêneos e de alto desempenho, tornam o projeto de tais sistemas mais complexo, exigindo mecanismos automatizados de exploração de espaço de projeto cientes de dark silicon. Uma solução promissora é a utilização da computação aproximada, na qual, componentes de hardware e software utilizam a aproximação ao invés da precisão das operações, aceitando perda de qualidade de saída para melhorar a eficiência energética e obter ganhos de desempenho. Este trabalho objetiva obter soluções eficientes para o problema de exploração de projetos de processadores cientes de dark silicon, utilizando módulos de computação aproximada como elementos factíveis de um sistema computacional heterogêneo.

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