Virtual Systolic Array for QR Decomposition

2013 IEEE 27th International Symposium on Parallel and Distributed Processing ◽

10.1109/ipdps.2013.119 ◽

2013 ◽

Cited By ~ 3

Author(s):

Jakub Kurzak ◽

Piotr Luszczek ◽

Mark Gates ◽

Ichitaro Yamazaki ◽

Jack Dongarra

Keyword(s):

Systolic Array ◽

Qr Decomposition

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Dataflow Systolic Array Implementations of Exploring Dual-Triangular Structure in QR Decomposition Using High-Level Synthesis

10.1109/icfpt52863.2021.9609814 ◽

2021 ◽

Author(s):

Siyang Jiang ◽

Hsi-Wen Chen ◽

Ming-Syan Chen

Keyword(s):

Systolic Array ◽

Qr Decomposition ◽

High Level Synthesis ◽

Triangular Structure ◽

High Level

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Systolic-array based regularized QR-decomposition for IEEE 802.11n compliant soft-MMSE detection

2010 International Conference on Microelectronics ◽

10.1109/icm.2010.5696169 ◽

2010 ◽

Cited By ~ 10

Author(s):

Christian Senning ◽

Andreas Staudacher ◽

Andreas Burg

Keyword(s):

Systolic Array ◽

Qr Decomposition ◽

Ieee 802.11N

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A configurable distributed systolic array for QR decomposition in MIMO-OFDM systems

2013 IEEE 10th International Conference on ASIC ◽

10.1109/asicon.2013.6812012 ◽

2013 ◽

Author(s):

Yongxu Zhu ◽

Bin Wu ◽

Yumei Zhou ◽

Kaifeng Xia ◽

Lu Sun

Keyword(s):

Systolic Array ◽

Qr Decomposition ◽

Ofdm Systems ◽

Mimo Ofdm

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An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC

2014 International Conference on Field-Programmable Technology (FPT) ◽

10.1109/fpt.2014.7082764 ◽

2014 ◽

Cited By ~ 3

Author(s):

Jianfeng Zhang ◽

Paul Chow ◽

Hengzhu Liu

Keyword(s):

Systolic Array ◽

Qr Decomposition ◽

Fpga Implementation ◽

Array Architecture

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Triangular systolic array with reduced latency for QR-decomposition of complex matrices

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1692603 ◽

2006 ◽

Cited By ~ 49

Author(s):

A. Maltsev ◽

V. Pestretsov ◽

R. Maslennikov ◽

A. Khoryaev

Keyword(s):

Systolic Array ◽

Qr Decomposition ◽

Complex Matrices

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Design and Implementation of a Large Scale Tree-Based QR Decomposition Using a 3D Virtual Systolic Array and a Lightweight Runtime

2014 IEEE International Parallel & Distributed Processing Symposium Workshops ◽

10.1109/ipdpsw.2014.167 ◽

2014 ◽

Cited By ~ 1

Author(s):

Ichitaro Yamazaki ◽

Jakub Kurzak ◽

Piotr Luszczek ◽

Jack Dongarra

Keyword(s):

Systolic Array ◽

Large Scale ◽

Qr Decomposition ◽

Design And Implementation

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A truly two-dimensional systolic array FPGA implementation of QR decomposition

ACM Transactions on Embedded Computing Systems ◽

10.1145/1596532.1596535 ◽

2009 ◽

Vol 9 (1) ◽

pp. 1-17 ◽

Cited By ~ 15

Author(s):

Xiaojun Wang ◽

Miriam Leeser

Keyword(s):

Systolic Array ◽

Qr Decomposition ◽

Fpga Implementation ◽

Two Dimensional

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A Distributed Systolic Array Processing Algorithm for QR-decomposition in MIMO-OFDM System

JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY ◽

10.3724/sp.j.1146.2011.00768 ◽

2013 ◽

Vol 34 (8) ◽

pp. 1968-1973

Author(s):

Yong-xu Zhu ◽

Bin Wu ◽

Yu-mei Zhou ◽

Jing-jing Cai ◽

Kai-feng Xia

Keyword(s):

Systolic Array ◽

Array Processing ◽

Qr Decomposition ◽

Processing Algorithm ◽

Ofdm System ◽

Mimo Ofdm

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Efficient FPGA implementation of a High throughput systolic array QR-decomposition algorithm

2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR) ◽

10.1109/acssc.2011.6190140 ◽

2011 ◽

Cited By ~ 6

Author(s):

Matthias Abels ◽

Till Wiegand ◽

Steffen Paul

Keyword(s):

High Throughput ◽

Systolic Array ◽

Qr Decomposition ◽

Fpga Implementation ◽

Decomposition Algorithm

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CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition

ACM Transactions on Reconfigurable Technology and Systems ◽

10.1145/2827700 ◽

2016 ◽

Vol 9 (2) ◽

pp. 1-22 ◽

Cited By ~ 4

Author(s):

Jianfeng Zhang ◽

Paul Chow ◽

Hengzhu Liu

Keyword(s):

Systolic Array ◽

Qr Decomposition ◽

Array Architecture

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