CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition

2016 ◽  
Vol 9 (2) ◽  
pp. 1-22 ◽  
Author(s):  
Jianfeng Zhang ◽  
Paul Chow ◽  
Hengzhu Liu
Keyword(s):  
Systolic Array ◽  
Qr Decomposition ◽  
Array Architecture

scholarly journals Design and Implementation of a Large Scale Tree-Based QR Decomposition Using a 3D Virtual Systolic Array and a Lightweight Runtime

2014 ◽  
Vol 24 (04) ◽  
pp. 1442004
Author(s):  
Ichitaro Yamazaki ◽  
Jakub Kurzak ◽  
Piotr Luszczek ◽  
Jack Dongarra
Keyword(s):  
Integrated Circuits ◽  
Systolic Array ◽  
Large Scale ◽  
Three Dimensional ◽  
Qr Decomposition ◽  
Dense Matrix ◽  
Von Neumann ◽  
Computing Paradigm ◽  
Array Architecture ◽  
Von Neumann Architecture

A systolic array provides an alternative computing paradigm to the von Neumann architecture. Though its hardware implementation has failed as a paradigm to design integrated circuits in the past, we are now discovering that the systolic array as a software virtualization layer can lead to an extremely scalable execution paradigm. To demonstrate this scalability, in this paper, we design and implement a 3D virtual systolic array to compute a tile QR decomposition of a tall-and-skinny dense matrix. Our implementation is based on a state-of-the-art algorithm that factorizes a panel based on a tree-reduction. Freed from the constraint of a planar layout, we present a three-dimensional virtual systolic array architecture for this algorithm. Using a runtime developed as a part of the Parallel Ultra Light Systolic Array Runtime (PULSAR) project, we demonstrate on a Cray-XT5 machine how our virtual systolic array can be mapped to a large-scale machine and obtain excellent parallel performance. This is an important contribution since such a QR decomposition is used, for example, to compute a least squares solution of an overdetermined system, which arises in many scientific and engineering problems.

A systolic array architecture for the Applebaum-Howells array

1990 ◽  
Vol 38 (8) ◽  
pp. 1310-1313 ◽  
Author(s):  
M. Ueno ◽  
K. Kawabata ◽  
T. Morooka
Keyword(s):  
Systolic Array ◽  
Array Architecture
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