A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity

2007 IEEE International Parallel and Distributed Processing Symposium ◽

10.1109/ipdps.2007.370528 ◽

2007 ◽

Cited By ~ 1

Author(s):

Engin Ipek ◽

Meyrem Kirman ◽

Nevin Kirman ◽

Jose F. Martinez

Keyword(s):

Chip Multiprocessor ◽

Software Diversity ◽

Multiprocessor Architecture

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Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture

Languages and Compilers for Parallel Computing - Lecture Notes in Computer Science ◽

10.1007/978-3-540-85261-2_18 ◽

2008 ◽

pp. 261-275

Author(s):

Slo-Li Chu

Keyword(s):

Block Scheduling ◽

Chip Multiprocessor ◽

Multiprocessor Architecture

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P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA

Wireless Personal Communications ◽

10.1007/s11277-020-07529-2 ◽

2020 ◽

Vol 114 (4) ◽

pp. 3295-3319

Author(s):

Khyamling Parane ◽

B. M. Prabhu Prasad ◽

Basavaraj Talawar

Keyword(s):

Performance Evaluation ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Chip Multiprocessor ◽

Multiprocessor Architecture

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A novel 3D crossbar-based chip multiprocessor architecture

2013 Second International Japan-Egypt Conference on Electronics, Communications and Computers (JEC-ECC) ◽

10.1109/jec-ecc.2013.6766390 ◽

2013 ◽

Author(s):

Mostafa Mahmoud ◽

Amr Wassal

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture

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An on-chip multiprocessor architecture with a non-blocking synchronization mechanism

Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium ◽

10.1109/eurmic.1999.794505 ◽

1999 ◽

Cited By ~ 3

Author(s):

R. Kobayashi ◽

M. Iwata ◽

Y. Ogawa ◽

H. Ando ◽

T. Shimada

Keyword(s):

Chip Multiprocessor ◽

Synchronization Mechanism ◽

Multiprocessor Architecture ◽

On Chip

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Fair cache sharing and partitioning in a chip multiprocessor architecture

Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004. ◽

10.1109/pact.2004.1342546 ◽

2004 ◽

Cited By ~ 70

Author(s):

Seongbeom Kim ◽

D. Chandra ◽

Yan Solihin

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture

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A complete strategy for testing an on-chip multiprocessor architecture

IEEE Design & Test of Computers ◽

10.1109/54.980050 ◽

2002 ◽

Vol 19 (1) ◽

pp. 18-28 ◽

Cited By ~ 36

Author(s):

C. Aktouf

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture ◽

On Chip

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An Isometric on on-Chip Multiprocessor Architecture

2007 14th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2007.4511159 ◽

2007 ◽

Cited By ~ 1

Author(s):

Etienne Ogoubi ◽

Abdel Hakim Hafid ◽

Marcel Turcotte

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture ◽

On Chip

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A chip-multiprocessor architecture with speculative multithreading

IEEE Transactions on Computers ◽

10.1109/12.795218 ◽

1999 ◽

Vol 48 (9) ◽

pp. 866-880 ◽

Cited By ~ 177

Author(s):

V. Krishnan ◽

J. Torrellas

Keyword(s):

Chip Multiprocessor ◽

Speculative Multithreading ◽

Multiprocessor Architecture

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Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency

Synthesis Lectures on Computer Architecture ◽

10.2200/s00093ed1v01y200707cac003 ◽

2007 ◽

Vol 2 (1) ◽

pp. 1-145 ◽

Cited By ~ 26

Author(s):

Kunle Olukotun ◽

Lance Hammond ◽

James Laudon

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture

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Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture

High Performance Computing and Communications - Lecture Notes in Computer Science ◽

10.1007/11557654_27 ◽

2005 ◽

pp. 213-222 ◽

Cited By ~ 2

Author(s):

Francisco J. Villa ◽

Manuel E. Acacio ◽

José M. García

Keyword(s):

Chip Multiprocessor ◽

Memory Subsystem ◽

Multiprocessor Architecture

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