A complete strategy for testing an on-chip multiprocessor architecture

C. Aktouf

doi:10.1109/54.980050

A complete strategy for testing an on-chip multiprocessor architecture

IEEE Design & Test of Computers ◽

10.1109/54.980050 ◽

2002 ◽

Vol 19 (1) ◽

pp. 18-28 ◽

Cited By ~ 36

Author(s):

C. Aktouf

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture ◽

On Chip

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An on-chip multiprocessor architecture with a non-blocking synchronization mechanism

Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium ◽

10.1109/eurmic.1999.794505 ◽

1999 ◽

Cited By ~ 3

Author(s):

R. Kobayashi ◽

M. Iwata ◽

Y. Ogawa ◽

H. Ando ◽

T. Shimada

Keyword(s):

Chip Multiprocessor ◽

Synchronization Mechanism ◽

Multiprocessor Architecture ◽

On Chip

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An Isometric on on-Chip Multiprocessor Architecture

2007 14th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2007.4511159 ◽

2007 ◽

Cited By ~ 1

Author(s):

Etienne Ogoubi ◽

Abdel Hakim Hafid ◽

Marcel Turcotte

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Architecture ◽

On Chip

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Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.23919/date.2019.8715267 ◽

2019 ◽

Cited By ~ 2

Author(s):

Kaiwei Zou ◽

Ying Wang ◽

Huawei Li ◽

Xiaowei Li

Keyword(s):

Deep Learning ◽

Chip Multiprocessor ◽

Multiprocessor Architecture ◽

On Chip

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GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications

Architecture of Computing Systems - ARCS 2006 - Lecture Notes in Computer Science ◽

10.1007/11682127_19 ◽

2006 ◽

pp. 268-282 ◽

Cited By ~ 3

Author(s):

Jörg-Christian Niemann ◽

Christoph Puttmann ◽

Mario Porrmann ◽

Ulrich Rückert

Keyword(s):

Chip Multiprocessor ◽

Network Applications ◽

Multiprocessor Architecture ◽

On Chip

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Application-driven architecture synthesis of on-chip Multiprocessor systems

2010 International Conference on High Performance Computing & Simulation ◽

10.1109/hpcs.2010.5547070 ◽

2010 ◽

Author(s):

C Bobda ◽

P Mahr ◽

B Andres ◽

H Ishebabi

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Systems ◽

On Chip

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Hardware/software support for adaptive work-stealing in on-chip multiprocessor

Journal of Systems Architecture ◽

10.1016/j.sysarc.2010.06.007 ◽

2010 ◽

Vol 56 (8) ◽

pp. 392-406 ◽

Cited By ~ 1

Author(s):

Quentin Meunier ◽

Frédéric Pétrot ◽

Jean-Louis Roch

Keyword(s):

Chip Multiprocessor ◽

Work Stealing ◽

Software Support ◽

On Chip ◽

Adaptive Work

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Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance

10.17918/00000254 ◽

2020 ◽

Author(s):

Karthik Sangaiah

Keyword(s):

Network On Chip ◽

Chip Multiprocessor ◽

On Chip

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Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture

Languages and Compilers for Parallel Computing - Lecture Notes in Computer Science ◽

10.1007/978-3-540-85261-2_18 ◽

2008 ◽

pp. 261-275

Author(s):

Slo-Li Chu

Keyword(s):

Block Scheduling ◽

Chip Multiprocessor ◽

Multiprocessor Architecture

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Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms

Journal of Computer Science and Technology ◽

10.1007/s11390-013-1409-2 ◽

2014 ◽

Vol 29 (1) ◽

pp. 21-37 ◽

Cited By ~ 2

Author(s):

Fang Lv ◽

Hui-Min Cui ◽

Lei Wang ◽

Lei Liu ◽

Cheng-Gang Wu ◽

...

Keyword(s):

Chip Multiprocessor ◽

Multiprocessor Systems ◽

Batch Mode ◽

On Chip

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Dynamic Parallelization of Array Based On-Chip Multiprocessor Applications

Embedded Software for SoC ◽

10.1007/0-306-48709-8_23 ◽

2005 ◽

pp. 305-318

Author(s):

M. Kandemir ◽

W. Zhang ◽

M. Karakoy

Keyword(s):

Chip Multiprocessor ◽

On Chip

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