A NoC-Based High Performance Deadlock Avoidance Routing Algorithm

2008 ◽  
Author(s):  
Zhaohui Song ◽  
Guangsheng Ma ◽  
Dalei Song
Keyword(s):  
High Performance ◽  
Routing Algorithm ◽  
Deadlock Avoidance

On the Configuration of Switch-Based Networks with Wormhole Routing

2000 ◽  
Vol 01 (02) ◽  
pp. 95-114 ◽  
Author(s):  
Wan Y. Lee ◽  
Sung Je Hong ◽  
Jong Kim
Keyword(s):  
High Performance ◽  
Average Distance ◽  
Routing Algorithm ◽  
Wormhole Routing ◽  
Deadlock Avoidance ◽  
Network Resources ◽  
Communication Performance ◽  
Minimum Number ◽  
Network Properties ◽  
Routing Tables

In this paper we investigate the configuration of switches suitable for high performance communication, and propose communication schemes which exploit the structural strengths of that configuration. In switch-based networks, communication performance heavily depends on the configuration of switches and communication schemes for the networks. The deadlock problem caused by wormhole routing is another crucial factor affecting communication performance. Thus, we first evaluate several candidate configurations in terms of deadlock avoidance, scalability, flexibility, cost, and network properties (bandwidth, diameter, and average distance), and verify that the incomplete fat tree is the most promising configuration. Next, we show how to implement a routing algorithm and a unicast-based multicast algorithm on the incomplete fat tree configuration. The routing algorithm always finds a shortest path and fully utilizes network resources without using a routing tables. The multicast algorithm is optimal in that it is contention-free and requires a minimum number of communication steps.

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

scholarly journals Framework for Design Exploration and Performance Analysis of RF-NoC Manycore Architecture

2020 ◽  
Vol 10 (4) ◽  
pp. 37
Author(s):  
Habiba Lahdhiri ◽  
Jordane Lorandel ◽  
Salvatore Monteleone ◽  
Emmanuelle Bourdel ◽  
Maurizio Palesi
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Routing Algorithm ◽  
Long Distance ◽  
Promising Solution ◽  
And Performance ◽  
On Chip ◽  
Many Core ◽  
High Degree ◽  
Real Traffic

The Network-on-chip (NoC) paradigm has been proposed as a promising solution to enable the handling of a high degree of integration in multi-/many-core architectures. Despite their advantages, wired NoC infrastructures are facing several performance issues regarding multi-hop long-distance communications. RF-NoC is an attractive solution offering high performance and multicast/broadcast capabilities. However, managing RF links is a critical aspect that relies on both application-dependent and architectural parameters. This paper proposes a design space exploration framework for OFDMA-based RF-NoC architecture, which takes advantage of both real application benchmarks simulated using Sniper and RF-NoC architecture modeled using Noxim. We adopted the proposed framework to finely configure a routing algorithm, working with real traffic, achieving up to 45% of delay reduction, compared to a wired NoC setup in similar conditions.

scholarly journals A High Performance Global Routing Algorithm on Julia Parallel Computing Platform

2021 ◽  
Vol 9 ◽  
pp. 103-108
Author(s):  
Meenakshi Agarwalla ◽  
Manash Pratim Sarma ◽  
Kandarpa Kumar Sarma
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Routing Algorithm ◽  
Global Routing ◽  
Careful Attention ◽  
Additional Advantage ◽  
C Language ◽  
Computing Platform ◽  
Sequential Processing ◽  
Design Requirements

o keep pace with the design requirements of Integrated Circuits (ICs), parallel processing is adopted. The path to be routed between two nodes may or may not be dependent on the previously routed paths. The solution requires careful attention in distributing the nets to be routed to different processors. Previous work on allocating the tasks to processors has been quite successful, reporting upto 3x improvement on 4 cores and 5x improvement on 8 core machine. The advantage of increasing the number of cores diminishes with each added processor and the challenge lies in being able to maintain the improvement per added core. The existing techniques of distributing the nets cannot provide additional advantage of using more than 8 cores. This paper improves the work on parallelizing global routing using a technique of balancing the load on the processors for better utilization of the resources. A relatively new budding platform Julia has been used which provides the ease of programming while maintaining the performance of the C language. Technique used in this paper has enabled to use 16 cores with routing solutions obtained in 0.8 minutes achieving 12.5 times speedup compared to sequential processing on a single core

scholarly journals Reconfigurable High Performance Secured NoC Design Using Hierarchical Agent-based Monitoring System

2018 ◽  
Vol 8 (6) ◽  
pp. 4164
Author(s):  
Kendaganna Swamy S ◽  
Anand Jatti ◽  
Uma B. V
Keyword(s):  
Monitoring System ◽  
High Performance ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Data Communication ◽  
Multiprocessor System ◽  
Packet Routing ◽  
Distributed Agents ◽  
Agent Based ◽  
On Chip

With the rapid increase in demand for high performance computing, there is also a significant growth of data communication that leads to leverage the significance of network on chip. This paper proposes a reconfigurable fault tolerant on chip architecture with hierarchical agent based monitoring system for enhancing the performance of network based multiprocessor system on chip against faulty links and nodes. These distributed agents provide healthy status and congestion information of the network. This status information is used for further packet routing in the network with the help of XY routing algorithm. The functionality of Agent is enhanced not only to work as information provider but also to take decision for packet to either pass or stop to the processing element by setting the firewall in order to provide security. Proposed design provides a better performance and area optimization by avoiding deadlock and live lock as compared to existing approaches over network design.

Reducing the number of passing links in the 2D-NoC for performance and reliability improvement

2020 ◽  
Vol 17 (5) ◽  
pp. 621-632
Author(s):  
Seyyed Javad Seyyed Mahdavi Chabok ◽  
Seyed Amin Alavi
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Network Reliability ◽  
Telecommunication Network ◽  
High Reliability ◽  
Routing Algorithm ◽  
Network Size ◽  
Content Type ◽  
Probability Of Collision ◽  
On Chip

Purpose The routing algorithm is one of the most important components in designing a network-on-chip (NoC). An effective routing algorithm can cause better performance and throughput, and thus, have less latency, lower power consumption and high reliability. Considering the high scalability in networks and fault occurrence on links, the more the packet reaches the destination (i.e. to cross the number of fewer links), the less the loss of packets and information would be. Accordingly, the proposed algorithm is based on reducing the number of passed links to reach the destination. Design/methodology/approach This paper presents a high-performance NoC that increases telecommunication network reliability by passing fewer links to destination. A large NoC is divided into small districts with central routers. In such a system, routing in large routes is performed through these central routers district by district. Findings By reducing the number of links, the number of routers also decreases. As a result, the power consumption is reduced, the performance of the NoC is improved, and the probability of collision with a faulty link and network latency is decreased. Originality/value The simulation is performed using the Noxim simulator because of its ability to manage and inject faults. The proposed algorithm, XY routing, as a conventional algorithm for the NoC, was simulated in a 14 × 14 network size, as the typical network size in the recent works.

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