Failure analysis of lead-free solder joints for flip chip on board

2007 ◽  
Author(s):  
Fu-Ming Tzu ◽  
Long-Sun Chao ◽  
Jung-Hua Chou
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Joints ◽  
Lead Free ◽  
Lead Free Solder ◽  
Free Solder

Failure analysis techniques for lead‐free solder joints

2006 ◽  
Vol 18 (4) ◽  
pp. 21-27 ◽  
Author(s):  
Todd Castello ◽  
Dan Rooney ◽  
Dongkai Shangguan
Keyword(s):  
Failure Analysis ◽  
Solder Joints ◽  
Lead Free ◽  
Lead Free Solder ◽  
Analysis Techniques ◽  
Free Solder

Failure Analysis of Lead-Free Solder Joints of an 1657CCGA (Ceramic Column Grid Array) Package

2007 ◽  
Vol 4 (3) ◽  
pp. 112-120 ◽  
Author(s):  
John Lau ◽  
Todd Castello ◽  
Dongkai Shangguan ◽  
Walter Dauksher ◽  
Joe Smetana ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Surface Finish ◽  
Failure Modes ◽  
Solder Joints ◽  
Temperature Cycling ◽  
Lead Free ◽  
Lead Free Solder ◽  
Organic Solderability Preservative ◽  
Solder Pastes ◽  
Free Solder

In this study, failure analysis of the 1657CCGA package with 95.5wt%Sn3.9wt%Ag0.6wt%Cu and 63wt%Sn37wt%Pb solder pastes on lead-free PCBs with the Entek OSP (organic solderability preservative) surface finish is investigated. Emphasis is placed on determining the failure locations and failure modes of the solder joints of the 1657CCGA assemblies after they have been through 7,000 cycles of temperature cycling.

Failure mechanism of lead-free solder joints in flip chip packages

2002 ◽  
Vol 31 (11) ◽  
pp. 1256-1263 ◽  
Author(s):  
Fan Zhang ◽  
Ming Li ◽  
Bavani Balakrisnan ◽  
William T. Chen
Keyword(s):  
Failure Mechanism ◽  
Flip Chip ◽  
Solder Joints ◽  
Lead Free ◽  
Lead Free Solder ◽  
Free Solder

Parametric study on flip chip package with lead-free solder joints by using the probabilistic designing approach

2004 ◽  
Vol 44 (12) ◽  
pp. 1947-1955 ◽  
Author(s):  
D.G. Yang ◽  
J.S. Liang ◽  
Q.Y. Li ◽  
L.J. Ernst ◽  
G.Q. Zhang
Keyword(s):  
Parametric Study ◽  
Flip Chip ◽  
Solder Joints ◽  
Lead Free ◽  
Lead Free Solder ◽  
Free Solder

Characterization of Die Stresses in CBGA Packages due to Component Assembly and Heat Sink Clamping

2011 ◽  
Author(s):  
Jordan C. Roberts ◽  
Mohammad Motalab ◽  
Safina Hussain ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
...  
Keyword(s):  
Heat Sink ◽  
Flip Chip ◽  
Solder Joints ◽  
Ceramic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Interconnects ◽  
Die Stress ◽  
Free Solder ◽  
Test Chips

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level CBGA solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, we have used test chips containing piezoresistive sensors to measure the buildup of mechanical stresses in a microprocessor die after various steps of the CBGA assembly process, as well as due to heat sink clamping. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses have been found to increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, lid attachment, CBGA assembly to PCB, and heat sink clamping). Levels exceeding 500 MPa have been observed for extremely high heat sink clamping forces. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the individual test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. A metallic lid and second level solder balls were attached to complete the flip chip ceramic BGA components. After every packaging step (flip chip solder ball reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. Finally, CBGAs with the stress sensing chips were soldered to organic PCB test boards. A simulated heat sink loading was then applied, and the stresses were measured as a function of the clamping force. The heat sink clamping pressure distribution was monitored using in-situ resistive sensors in the TIM2 position between the lid and heat sink. The measured stress changes due to heat sink clamping where correlated with finite element simulations. With suitable detail in the models, excellent correlation has been obtained.

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